HD64F7047FW40V Renesas Electronics America, HD64F7047FW40V Datasheet - Page 65

• Manufacturer Part Number: HD64F7047FW40V
• Description: MCU 5V 256K I-TEMP,PB-FREE 100-Q
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047FW40V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

2.4.2
Table 2.8 describes addressing modes and effective address calculation.
Table 2.8
Addressing
Mode
Direct register
addressing
Indirect register
addressing
Post-increment
indirect register
addressing
Pre-decrement
indirect register
addressing
Addressing Modes
Addressing Modes and Effective Addresses
Instruction
Format
Rn
@Rn
@Rn+
@-Rn
Effective Address Calculation
The effective address is register Rn. (The operand
is the contents of register Rn.)
The effective address is the contents of register Rn.
The effective address is the contents of register Rn.
A constant is added to the content of Rn after the
instruction is executed. 1 is added for a byte
operation, 2 for a word operation, and 4 for a
longword operation.
The effective address is the value obtained by
subtracting a constant from Rn. 1 is subtracted for
a byte operation, 2 for a word operation, and 4 for
a longword operation.
1/2/4
1/2/4
Rn
Rn
Rn
Rn + 1/2/4
Rn – 1/2/4
+
–
Rn – 1/2/4
Rev. 2.00, 09/04, page 23 of 720
Rn
Rn
Equation

Rn
Rn
(After the
instruction
executes)
Byte:
Rn + 1 → Rn
Word:
Rn + 2 → Rn
Longword:
Rn + 4 → Rn
Byte:
Rn – 1 → Rn
Word:
Rn – 2 → Rn
Longword:
Rn – 4 → Rn
(Instruction is
executed
with Rn after
this
calculation)