HD64F7047FW40V Renesas Electronics America, HD64F7047FW40V Datasheet - Page 573

• Manufacturer Part Number: HD64F7047FW40V
• Description: MCU 5V 256K I-TEMP,PB-FREE 100-Q
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047FW40V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

The initial value of PDIORL is H'0000.
17.1.6
The port D control registers L1 and L2 (PDCRL1 and PDCRL2) are 16-bit readable/writable
registers that are used to select the multiplexed pin function of the pins on port D.
Port D Control Registers L1 and L2 (PDCRL1 and PDCRL2)
Register
PDCRL2
PDCRL1
PDCRL2
PDCRL1
PDCRL2
PDCRL1
PDCRL2
PDCRL1
PDCRL2
PDCRL1
PDCRL2
PDCRL1
PDCRL2
PDCRL1
Port D Control Registers L1 and L2 (PDCRL1 and PDCRL2)
Bit
15 to 9
15 to 9
8
8
7
7
6
6
5
5
4
4
3
3
Bit Name


PD8MD1
PD8MD0
PD7MD1
PD7MD0
PD6MD1
PD6MD0
PD5MD1
PD5MD0
PD4MD1
PD4MD0
PD3MD1
PD3MD0
Initial
Value
All 0
All 0
0
0
0
0*
0
0*
0
0*
0
0*
0
0*
2
2
2
2
2
R/W
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved
These bits are always read as 0 and should only be
written with 0.
PD8 Mode
Select the function of the PD8/UBCTRG pin.
00: PD8 I/O (port)
01: Setting prohibited
PD7 Mode
Select the function of the PD7/D7/AUDSYNC pin.
00: PD7 I/O (port)
01: D7 I/O (BSC)
PD6 Mode
Select the function of the PD6/D6/AUDCK pin.
00: PD6 I/O (port)
01: D6 I/O (BSC)
PD5 Mode
Select the function of the PD5/D5/AUDMD pin.
00: PD5 I/O (port)
01: D5 I/O (BSC)
PD4 Mode
Select the function of the PD4/D4/AUDRST pin.
00: PD4 I/O (port)
01: D4 I/O (BSC)
PD3 Mode
Select the function of the PD3/D3/AUDATA3 pin.
00: PD3 I/O (port)
01: D3 I/O (BSC)
Rev. 2.00, 09/04, page 531 of 720
10: Setting prohibited
11: UBCTRG output (UBC)*
10: Setting prohibited
11: AUDSYNC I/O (AUD)*
10: Setting prohibited
11: AUDCK I/O (AUD)*
10: Setting prohibited
11: AUDMD input (AUD)*
10: Setting prohibited
11: AUDRST input (AUD)*
10: Setting prohibited
11: AUDATA3 I/O (AUD)*
1
1
1
1
1
1