HD64F7047FW40V Renesas Electronics America, HD64F7047FW40V Datasheet - Page 496
HD64F7047FW40V
Manufacturer Part Number
HD64F7047FW40V
Description
MCU 5V 256K I-TEMP,PB-FREE 100-Q
Manufacturer
Renesas Electronics America
Series
SuperH® SH7047r
Datasheet
1.HD64F7047F50V.pdf
(766 pages)
Specifications of HD64F7047FW40V
Core Processor
SH-2
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
53
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Table 15.3 Message Data Area Configuration in TCT Bit Setting
15.3.17 Timer Counter Register (TCNTR)
TCNTR is a 16-bit readable/writable register. This allows the CPU to monitor the timer counter
value and set the free-running timer counter value. Setting the TCR11 bit to 1 allows TCMR0 to
clear the timer when a timer value and TCMR0 (timer compare match 0) matched and the value is
set to LOSR (local offset register). Then counting starts.
Rev. 2.00, 09/04, page 454 of 720
Address 15 14 13 12 11 10 9
H'108 +
N*32
H'10A +
N*32
H'10C +
N*32
H'10E +
N*32
Bit
15 to 0 TCNTR15 to
Bit Name
TCNTR0
Cycle_Counter (first Rx/Tx Byte) MSG_DATA_1
TCNTR[7:0]
MSG_DATA_4
MSG_DATA_6
Initial
Value
All 0
R/W
R/W
Data Bus
8
Description
Timer Count Register
Setting bit 15 (TCR15) in the timer control register (TCR)
to 1 enables these bits to be used as a free-running
counter. The counter value can be cleared depending on
the compare match condition.
7
TCNTR[15:8]
MSG_DATA_5
MSG_DATA_7
6
5
4
3
2
1
0
Access
Size
Byte or
word
Field
Name
Data
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