HD64F7047FW40V Renesas Electronics America, HD64F7047FW40V Datasheet - Page 364

• Manufacturer Part Number: HD64F7047FW40V
• Description: MCU 5V 256K I-TEMP,PB-FREE 100-Q
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047FW40V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

11.4
11.4.1
To use the WDT as a watchdog timer, set the WT/IT and TME bits of TCSR to 1. Software must
prevent TCNT overflow by rewriting the TCNT value (normally by writing H'00) before overflow
occurs. No TCNT overflows will occur while the system is operating normally, but if TCNT fails
to be rewritten and overflows occur due to a system crash or the like, a WDTOVF signal is output
externally. The WDTOVF signal can be used to reset the system. The WDTOVF signal is output
for 128 φ clock cycles.
If the RSTE bit in RSTCSR is set to 1, a signal to reset the chip will be generated internally
simultaneous to the WDTOVF signal when TCNT overflows. Either a power-on reset or a manual
reset can be selected by the RSTS bit in RSTCSR. The internal reset signal is output for 512 φ
clock cycles.
When a WDT overflow reset is generated simultaneously with a reset input at the RES pin, the
RES reset takes priority, and the WOVF bit in RSTCSR is cleared to 0.
The following are not initialized by a WDT reset signal:
• POE (port output enable) of MTU and MMT registers
• PFC (pin function controller) registers
• I/O port registers
These registers are initialized only by an external power-on reset.
Rev. 2.00, 09/04, page 322 of 720
Operation
Watchdog Timer Mode