HD64F7047FW40V Renesas Electronics America, HD64F7047FW40V Datasheet - Page 551

MCU 5V 256K I-TEMP,PB-FREE 100-Q

HD64F7047FW40V

Manufacturer Part Number
HD64F7047FW40V
Description
MCU 5V 256K I-TEMP,PB-FREE 100-Q
Manufacturer
Renesas Electronics America
Series
SuperH® SH7047r
Datasheet

Specifications of HD64F7047FW40V

Core Processor
SH-2
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
53
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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16.8.2
Table16.5 shows the pin configuration of the POE circuit.
Table 16.5 Pin Configuration
16.8.3
The POE circuit has the following registers.
• Input level control/status register (ICSR2)
Input Level Control/Status Register (ICSR2): The input level control/status register (ICSR2) is
a 16-bit readable/writable register that selects the input mode for pins POE4 to POE6, controls
enabling or disabling of interrupts, and holds status information.
Name
Port output enable input pins
POE6
POE5
POE4
Input/Output Pins
Register Descriptions
Input level detection circuit
Pφ/8
detection circuit
detection circuit
Falling edge
Low level
Figure 16.18 Block Diagram of POE
Abbreviation
POE4 to POE6
Pφ/16
ICSR2
Pφ/128
I/O
Input
Input request signals for placing
MMT's output pins in high-impedance
state
Function
Rev. 2.00, 09/04, page 509 of 720
High impedance request
control signal
Interrupt request
(MMTPOE)

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