HD64F7047FW40V Renesas Electronics America, HD64F7047FW40V Datasheet - Page 177

MCU 5V 256K I-TEMP,PB-FREE 100-Q

HD64F7047FW40V

Manufacturer Part Number
HD64F7047FW40V
Description
MCU 5V 256K I-TEMP,PB-FREE 100-Q
Manufacturer
Renesas Electronics America
Series
SuperH® SH7047r
Datasheet

Specifications of HD64F7047FW40V

Core Processor
SH-2
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
53
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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9.2
Table 9.1 shows the bus state controller pin configuration.
Table 9.1
9.3
The BSC has four registers. For details on these register addresses and register states in each
processing states, refer to appendix A, Internal I/O Register.
These registers are used to control wait states, bus width, and interfaces with memories like ROM
and SRAM. All registers are 16 bits.
• Bus control register 1 (BCR1)
• Bus control register 2 (BCR2)
• Wait control register 1 (WCR1)
• RAM emulation register (RAMER)
Name
Address bus
Data bus
Chip select
Read
Lower write
Wait
Bus request
Bus acknowledge
Input/Output Pin
Register Configuration
Pin Configuration
Abbr.
A17 to A0
D7 to D0
CS0
RD
WRL
WAIT
BREQ
BACK
I/O
O
I/O
O
O
O
I
I
O
Description
Address output
8-bit data bus
Chip select signal indicating the area being
accessed
Strobe that indicates the read cycle
Strobe that indicates a write cycle to the lower 8
bits (D7 to D0)
Wait state request signal
Bus release request input
Bus use enable output
Rev. 2.00, 09/04, page 135 of 720

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