HD64F7047FW40V Renesas Electronics America, HD64F7047FW40V Datasheet - Page 178

MCU 5V 256K I-TEMP,PB-FREE 100-Q

HD64F7047FW40V

Manufacturer Part Number
HD64F7047FW40V
Description
MCU 5V 256K I-TEMP,PB-FREE 100-Q
Manufacturer
Renesas Electronics America
Series
SuperH® SH7047r
Datasheet

Specifications of HD64F7047FW40V

Core Processor
SH-2
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
53
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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9.4
Figure 9.2 shows the address format used by this LSI.
This chip uses 32-bit addresses:
• Bits A31 to A24 are used to select the type of space and are not output externally.
• Bits A23 and A22 are decoded and output as chip select signals (CS0) for the corresponding
• A17 to A0 are output externally. A21 to A18 are not output externally.
Table 9.2 shows the address map.
Rev. 2.00, 09/04, page 136 of 720
areas when bits A31 to A24 are 00000000.
A31 to A24
Address Map
Space selection:
Not output externally; used to select the type of space
On-chip ROM space or CS0 space when 00000000 (H'00)
Reserved (do not access) when 00000001 to 11111110 (H'01 to H'FE)
On-chip peripheral module space or on-chip RAM space when 11111111 (H'FF)
A23, A22
CS space selection:
Decoded, outputs CS0 when A31 to A24 = 00000000
Figure 9.2 Address Format
A21 to A18
A17
Output address:
Output from the address pins
A0

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