HD64F7047FW40V Renesas Electronics America, HD64F7047FW40V Datasheet - Page 547

MCU 5V 256K I-TEMP,PB-FREE 100-Q

HD64F7047FW40V

Manufacturer Part Number
HD64F7047FW40V
Description
MCU 5V 256K I-TEMP,PB-FREE 100-Q
Manufacturer
Renesas Electronics America
Series
SuperH® SH7047r
Datasheet

Specifications of HD64F7047FW40V

Core Processor
SH-2
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
53
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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16.7
16.7.1
MMT operation can be disabled or enabled using the module standby control register. The initial
setting is for MMT operation to be halted. Register access is enabled by clearing module standby
mode. For details, refer to section 24, Power-Down Modes.
16.7.2
Note that the kinds of operation and contention described below occur during MMT operation.
Contention between Buffer Register Write and Compare Match: If a compare match occurs in
the T2 state of a buffer register (TBRU to TBRW, or TPBR) write cycle, data is transferred from
the buffer register to the compare register (TGR or TPDR) by a buffer operation. The data
transferred is the buffer register write data.
Figure 16.15 shows the timing in this case.
Status flag
Interrupt
request signal
Address
Usage Notes
Module Standby Mode Setting
Notes for MMT Operation
Figure 16.14 Timing of Status Flag Clearing by DTC Controller
Source address
read cycle
T1
DTC
T2
Destination address
T1
write cycle
DTC
Rev. 2.00, 09/04, page 505 of 720
T2

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