HD64F7047FW40V Renesas Electronics America, HD64F7047FW40V Datasheet - Page 13

• Manufacturer Part Number: HD64F7047FW40V
• Description: MCU 5V 256K I-TEMP,PB-FREE 100-Q
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047FW40V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.4
6.5
6.6
6.7
6.8
Section 7 User Break Controller (UBC) ............................................................95
7.1
7.2
7.3
7.4
7.5
6.3.1
6.3.2
6.3.3
6.3.4
Interrupt Sources............................................................................................................... 82
6.4.1
6.4.2
6.4.3
6.4.4
Interrupt Exception Processing Vectors Table.................................................................. 84
Interrupt Operation............................................................................................................ 88
6.6.1
6.6.2
Interrupt Response Time................................................................................................... 91
Data Transfer with Interrupt Request Signals ................................................................... 93
6.8.1
6.8.2
6.8.3
Overview........................................................................................................................... 95
Register Descriptions ........................................................................................................ 97
7.2.1
7.2.2
7.2.3
7.2.4
Operation .......................................................................................................................... 101
7.3.1
7.3.2
7.3.3
Examples of Use ............................................................................................................... 104
Usage Notes ...................................................................................................................... 106
7.5.1
7.5.2
7.5.3
7.5.4
7.5.5
7.5.6
Interrupt Control Register 1 (ICR1)..................................................................... 76
Interrupt Control Register 2 (ICR2)..................................................................... 77
IRQ Status Register (ISR).................................................................................... 79
Interrupt Priority Registers A, D to I, K (IPRA, IPRD to IPRI, IPRK) ............... 80
External Interrupts ............................................................................................... 82
On-Chip Peripheral Module Interrupts ................................................................ 83
User Break Interrupt ............................................................................................ 83
H-UDI Interrupt ................................................................................................... 83
Interrupt Sequence ............................................................................................... 88
Stack after Interrupt Exception Processing .......................................................... 90
Handling Interrupt Request Signals as Sources for DTC
Activating and CPU Interrupt .............................................................................. 93
Handling Interrupt Request Signals as Source for DTC
Activating, but Not CPU Interrupt....................................................................... 94
Handling Interrupt Request Signals as Source for CPU
Interrupt but Not DTC Activating........................................................................ 94
User Break Address Register (UBAR) ................................................................ 97
User Break Address Mask Register (UBAMR) ................................................... 98
User Break Bus Cycle Register (UBBR) ............................................................. 98
User Break Control Register (UBCR) ................................................................. 100
Flow of the User Break Operation ....................................................................... 101
Break on On-Chip Memory Instruction Fetch Cycle ........................................... 103
Program Counter (PC) Values Saved................................................................... 103
Simultaneous Fetching of Two Instructions ........................................................ 106
Instruction Fetches at Branches ........................................................................... 106
Contention between User Break and Exception Processing ................................ 107
Break at Non-Delay Branch Instruction Jump Destination.................................. 107
User Break Trigger Output .................................................................................. 107
Module Standby Mode Setting ............................................................................ 108
Rev. 2.00, 09/04, page xi of xl