HD64F7047FW40V Renesas Electronics America, HD64F7047FW40V Datasheet - Page 33

• Manufacturer Part Number: HD64F7047FW40V
• Description: MCU 5V 256K I-TEMP,PB-FREE 100-Q
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047FW40V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Figure 15.4 Extended Format ..................................................................................................... 447
Figure 15.5 Hardware Reset Flowchart ...................................................................................... 461
Figure 15.6 Software Reset Flowchart........................................................................................ 462
Figure 15.7 Detailed Description of 1-Bit Time ......................................................................... 463
Figure 15.8 Transmission Flowchart by Event Trigger .............................................................. 466
Figure 15.9 Transmit Message Cancellation Flowchart ............................................................. 468
Figure 15.10 Flowchart in Reception ......................................................................................... 469
Figure 15.11 Unread Message Overwrite Flowchart .................................................................. 471
Figure 15.12 Change of Receive Box ID and Change from Receive Box to Transmit Box....... 473
Figure 15.13 HCAN2 Sleep Mode Flowchart ............................................................................ 474
Figure 15.14 HCAN2 Halt Mode Flowchart .............................................................................. 476
Figure 15.15 DTC Transfer Flowchart ....................................................................................... 478
Figure 15.16 High-Speed Interface Using HA13721.................................................................. 479
Section 16 Motor Management Timer (MMT)
Figure 16.1 Block Diagram of MMT.......................................................................................... 484
Figure 16.2 Sample Operating Mode Setting Procedure ............................................................ 492
Figure 16.3 Example of TCNT Count Operation ....................................................................... 493
Figure 16.4 Examples of Counter and Register Operations........................................................ 495
Figure 16.5 Example of PWM Waveform Generation ............................................................... 498
Figure 16.6 Example of TCNT Counter Clearing....................................................................... 499
Figure 16.7 Example of Toggle Output Waveform Synchronized with PWM Cycle................. 499
Figure 16.8 Count Timing .......................................................................................................... 501
Figure 16.9 TCNT Counter Clearing Timing ............................................................................. 501
Figure 16.10 TDCNT Operation Timing .................................................................................... 502
Figure 16.11 Buffer Operation Timing....................................................................................... 503
Figure 16.12 TGI Interrupt Timing............................................................................................. 504
Figure 16.13 Timing of Status Flag Clearing by CPU................................................................ 504
Figure 16.14 Timing of Status Flag Clearing by DTC Controller .............................................. 505
Figure 16.15 Contention between Buffer Register Write and Compare Match .......................... 506
Figure 16.16 Contention between Compare Register Write and Compare Match...................... 507
Figure 16.17 Writing into Timer General Registers (When One Cycle is Not Output).............. 508
Figure 16.18 Block Diagram of POE.......................................................................................... 509
Figure 16.19 Low Level Detection Operation ............................................................................ 512
Section 18 I/O Ports
Figure 18.1 Port A ...................................................................................................................... 537
Figure 18.2 Port B ...................................................................................................................... 539
Figure 18.3 Port D ...................................................................................................................... 541
Figure 18.4 Port E....................................................................................................................... 543
Figure 18.5 Port F ....................................................................................................................... 546
Section 19 Flash Memory (F-ZTAT Version)
Figure 19.1 Block Diagram of Flash Memory............................................................................ 550
Rev. 2.00, 09/04, page xxxi of xl