HD64F7047FW40V Renesas Electronics America, HD64F7047FW40V Datasheet - Page 612

• Manufacturer Part Number: HD64F7047FW40V
• Description: MCU 5V 256K I-TEMP,PB-FREE 100-Q
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047FW40V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

19.9.2
Software protection can be implemented against programming/erasing of all flash memory blocks
by clearing the SWE bit in FLMCR1. When software protection is in effect, setting the P or E bit
in FLMCR1 does not cause a transition to program mode or erase mode. By setting the erase block
register 1 (EBR1), erase protection can be set for individual blocks. When EBR1 is set to H'00,
erase protection is set for all blocks.
Item
SWE bit protect
Block protect
Emulation protect
19.9.3
In error protection, an error is detected when CPU runaway occurs during flash memory
programming/erasing, or operation is not performed in accordance with the program/erase
algorithm, and the program/erase operation is forcibly aborted. Aborting the program/erase
operation prevents damage to the flash memory due to overprogramming or overerasing.
When the following errors are detected during programming/erasing of flash memory, the FLER
bit in FLMCR2 is set to 1, and the error protection state is entered.
• When the flash memory is read during programming/erasing (including vector read and
• Immediately after exception handling (excluding a reset) during programming/erasing
• When a SLEEP instruction is executed during programming/erasing
The FLMCR1, FLMCR2, EBR1, and EBR2 settings are retained, however program mode or erase
mode is forcibly aborted at the point when the error is detected. Program mode or erase mode
cannot be re-entered by re-setting the P or E bit. However, PV and EV bit settings are retained,
and a transition can be made to verify mode. The error protection state can be cancelled by the
power-on reset only.
Rev. 2.00, 09/04, page 570 of 720
instruction fetch)
Software Protection
Error Protection
When the SWE bit in FLMCR1 is cleared to 0,
By setting the erase block register 1 (EBR1) and
Description
all blocks are program/erase-protected. (This
setting should be carried out in on-chip RAM or
external memory.)
the erase block register 2 (EBR2), erase
protection can be set for individual blocks.
When both EBR1 and EBR2 are set to H'00,
erase protection is set for all blocks.
When the RAMS bit in RAMER is set to 1, all
blocks are program/erase-protected.
Program
Yes

Yes
Protect Function
Erase
Yes
Yes
Yes