HD64F7047FW40V Renesas Electronics America, HD64F7047FW40V Datasheet - Page 244
HD64F7047FW40V
Manufacturer Part Number
HD64F7047FW40V
Description
MCU 5V 256K I-TEMP,PB-FREE 100-Q
Manufacturer
Renesas Electronics America
Series
SuperH® SH7047r
Datasheet
1.HD64F7047F50V.pdf
(766 pages)
Specifications of HD64F7047FW40V
Core Processor
SH-2
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
53
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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10.4.3
Buffer operation, provided for channels 0, 3, and 4, enables TGRC and TGRD to be used as buffer
registers.
Buffer operation differs depending on whether TGR has been designated as an input capture
register or as a compare match register.
Table 10.29 shows the register combinations used in buffer operation.
Table 10.29 Register Combinations in Buffer Operation
• When TGR is an output compare register
Rev. 2.00, 09/04, page 202 of 720
Channel
0
3
4
When a compare match occurs, the value in the buffer register for the corresponding channel is
transferred to the timer general register.
This operation is illustrated in figure 10.13.
Buffer Operation
register
Buffer
Figure 10.13 Compare Match Buffer Operation
Timer General Register
TGRA_0
TGRB_0
TGRA_3
TGRB_3
TGRA_4
TGRB_4
Compare match signal
Timer general
register
Comparator
Buffer Register
TGRC_0
TGRD_0
TGRC_3
TGRD_3
TGRC_4
TGRD_4
TCNT
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