HD64F7047FW40V Renesas Electronics America, HD64F7047FW40V Datasheet - Page 137

MCU 5V 256K I-TEMP,PB-FREE 100-Q

HD64F7047FW40V

Manufacturer Part Number
HD64F7047FW40V
Description
MCU 5V 256K I-TEMP,PB-FREE 100-Q
Manufacturer
Renesas Electronics America
Series
SuperH® SH7047r
Datasheet

Specifications of HD64F7047FW40V

Core Processor
SH-2
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
53
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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The user break controller (UBC) provides functions that make program debugging easier. By
setting break conditions in the UBC, a user break interrupt is generated according to the contents
of the bus cycle generated by the CPU or DTC. This function makes it easy to design an effective
self-monitoring debugger, and customers of the chip can easily debug their programs without
using a large in-circuit emulator.
7.1
• There are 5 types of break compare conditions as follows:
• User break interrupt generated upon satisfying break conditions
• User break interrupt generated before an instruction is executed by selecting break in the CPU
• Satisfaction of a break condition can be output to the UBCTRG pin.
• Module standby mode can be set
 Address
 CPU cycle or DTC cycle
 Instruction fetch or data access
 Read or write
 Operand size: longword/word/byte
instruction fetch.
Overview
Section 7 User Break Controller (UBC)
Rev. 2.00, 09/04, page 95 of 720

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