HD64F7047FW40V Renesas Electronics America, HD64F7047FW40V Datasheet - Page 546
HD64F7047FW40V
Manufacturer Part Number
HD64F7047FW40V
Description
MCU 5V 256K I-TEMP,PB-FREE 100-Q
Manufacturer
Renesas Electronics America
Series
SuperH® SH7047r
Datasheet
1.HD64F7047F50V.pdf
(766 pages)
Specifications of HD64F7047FW40V
Core Processor
SH-2
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
53
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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16.6.2
Timing of TGF Flag Setting by Compare Match: Figure 16.12 shows the timing of setting of
the TGF flag in the timer status register (TSR) on a compare match between TCNT and TPDR,
and the timing of the TGI interrupt request signal. The timing is the same for a compare match
between TCNT and 2Td.
Status Flag Clearing Timing: A status flag is cleared when the CPU reads 1 from the flag, then 0
is written to it. When the DTC controller is activated, the flag is cleared automatically. Figure
16.13 shows the timing of status flag clearing by the CPU, and figure 16.14 shows the timing of
status flag clearing by the DTC.
Rev. 2.00, 09/04, page 504 of 720
Interrupt Signal Timing
TCNT
TPDR
Compare match
signal
TGF flag
TGI interrupt
Pφ
Address
Write signal
Status flag
Interrupt
request
signal
Pφ
Figure 16.13 Timing of Status Flag Clearing by CPU
Figure 16.12 TGI Interrupt Timing
N – 3 N – 2 N – 1
TSR write cycle
T1
TSR address
N
N
T2
N + 1 N + 2 N + 3
N + 4
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