HD64F7047FW40V Renesas Electronics America, HD64F7047FW40V Datasheet - Page 175

MCU 5V 256K I-TEMP,PB-FREE 100-Q

HD64F7047FW40V

Manufacturer Part Number
HD64F7047FW40V
Description
MCU 5V 256K I-TEMP,PB-FREE 100-Q
Manufacturer
Renesas Electronics America
Series
SuperH® SH7047r
Datasheet

Specifications of HD64F7047FW40V

Core Processor
SH-2
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
53
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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The bus state controller (BSC) divides up the address spaces and outputs control for various types
of memory. This enables memories like SRAM and ROM to be linked directly to the chip without
external circuitry.
9.1
The BSC has the following features:
• Address space is divided into four spaces
• On-chip ROM and RAM interfaces
Figure 9.1 shows the BSC block diagram.
 A maximum linear 256-kbyte bus width (8 bits) for both on-chip ROM enabled mode and
 Wait states can be inserted by software for each space
 Wait state insertion with WAIT pin in external memory space access
 Outputs control signals for each space according to the type of memory connected
 On-chip ROM and RAM access of 32 bits in 1 state
on-chip ROM disabled mode, as for address space CS0
Features
Section 9 Bus State Controller (BSC)
Rev. 2.00, 09/04, page 133 of 720

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