HD64F7047FW40V Renesas Electronics America, HD64F7047FW40V Datasheet - Page 149

• Manufacturer Part Number: HD64F7047FW40V
• Description: MCU 5V 256K I-TEMP,PB-FREE 100-Q
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047FW40V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

7.5.3
If a user break is set for the fetch of a particular instruction, and exception processing with higher
priority than a user break is in contention and is accepted in the decode stage for that instruction
(or the next instruction), user break exception processing may not be performed after completion
of the higher-priority exception service routine (on return by RTE).
Thus, if a user break condition is specified to the branch destination instruction fetch after a
branch (BRA, BRAF, BT, BF, BT/S, BF/S, BSR, BSRF, JMP, JSR, RTS, RTE, exception
processing), and that branch instruction accepts an exception processing with higher priority than a
user break interrupt, user break exception processing is not performed after completion of the
exception service routine.
Therefore, a user break condition should not be set for the fetch of the branch destination
instruction after a branch.
7.5.4
When a branch instruction without delay slot (including exception processing) jumps to the
destination instruction by executing the branch, a user break will not be generated even if a user
break condition has been set for the first jump destination instruction fetch.
7.5.5
Information on internal bus condition matches monitored by the UBC is output as UBCTRG. The
trigger width can be set with clock select bits 1 and 0 (CKS1, CKS0) in the user break control
register (UBCR).
If a condition match occurs again during trigger output, the UBCTRG pin continues to output a
low level, and outputs a pulse of the length set in bits CKS1 and CKS0 from the cycle in which the
last condition match occurs.
The trigger output conditions differ from those in the case of a user break interrupt when a CPU
instruction fetch condition is satisfied. When a condition match occurs in an overrun fetch
instruction as described in Section 7.5.2, Instruction Fetch at Branches, a user break interrupt is
not requested but a trigger is output from the UBCTRG pin.
In other CPU data accesses and DTC bus cycles, pulse is output under the conditions similar to
user break interrupt conditions.
Setting the user break interrupt disable (UBID) bit to 1 in UBCR enables trigger output to be
monitored externally without requesting a user break interrupt.
Contention between User Break and Exception Processing
Break at Non-Delay Branch Instruction Jump Destination
User Break Trigger Output
Rev. 2.00, 09/04, page 107 of 720