HD64F7047FW40V Renesas Electronics America, HD64F7047FW40V Datasheet - Page 142

MCU 5V 256K I-TEMP,PB-FREE 100-Q

HD64F7047FW40V

Manufacturer Part Number
HD64F7047FW40V
Description
MCU 5V 256K I-TEMP,PB-FREE 100-Q
Manufacturer
Renesas Electronics America
Series
SuperH® SH7047r
Datasheet

Specifications of HD64F7047FW40V

Core Processor
SH-2
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
53
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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7.2.4
The user break control register (UBCR) is a 16-bit readable/writable register that (1) enables or
disables user break interrupts and (2) sets the pulse width of the UBCTRG signal output in the
event of a break condition match.
Rev. 2.00, 09/04, page 100 of 720
Bit
15 to 3
2
1
0
User Break Control Register (UBCR)
Bit Name
CKS1
CKS0
UBID
Initial
Value
All 0
0
0
0
R/W
R
R/W
R/W
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Clock Select 1 and 0
These bits specify the pulse width of the UBCTRG
signal output in the event of a condition match.
00: UBCTRG pulse width is φ
01: UBCTRG pulse width is φ/4
10: UBCTRG pulse width is φ/8
11: UBCTRG pulse width is φ/16
Note: φ means internal clock
User Break Disable
Enables or disables user break interrupt request
generation in the event of a user break condition
match.
0: User break interrupt request is enabled
1: User break interrupt request is disabled

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