HD64F7047FW40V Renesas Electronics America, HD64F7047FW40V Datasheet - Page 63

• Manufacturer Part Number: HD64F7047FW40V
• Description: MCU 5V 256K I-TEMP,PB-FREE 100-Q
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047FW40V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Multiply/Multiply-and-Accumulate Operations: 16-bit × 16-bit → 32-bit multiply operations
are executed in one to two states. 16-bit × 16-bit + 64-bit → 64-bit multiply-and-accumulate
operations are executed in two to three states. 32-bit × 32-bit → 64-bit multiply and 32-bit × 32-bit
+ 64-bit → 64-bit multiply-and-accumulate operations are executed in two to four states.
T Bit: The T bit in the status register changes according to the result of the comparison. Whether a
conditional branch is taken or not taken depends upon the T bit condition (true/false). The number
of instructions that change the T bit is kept to a minimum to improve the processing speed.
Table 2.4
Immediate Data: Byte (8-bit) immediate data is located in an instruction code. Word or longword
immediate data is not located in instruction codes but in a memory table. An immediate data
transfer instruction (MOV) accesses the memory table using the PC relative addressing mode with
displacement.
Table 2.5
Note: @(disp, PC) accesses the immediate data.
CPU of This LSI
CMP/GE
BT
BF
ADD
CMP/EQ
BT
Classification
8-bit immediate
16-bit immediate
32-bit immediate
R1,R0
TRGET0
TRGET1
#–1,R0
#0,R0
TRGET
T Bit
Immediate Data Accessing
CPU of This LSI
MOV
MOV.W
.DATA.W
MOV.L
.DATA.L
Description
T bit is set when R0 ≥ R1. The
program branches to TRGET0
when R0 ≥ R1 and to TRGET1
when R0 < R1.
T bit is not changed by ADD.
T bit is set when R0 = 0. The
program branches if R0 = 0.
#H'12,R0
@(disp,PC),R0
.................
H'1234
@(disp,PC),R0
.................
H'12345678
Example of Conventional CPU
MOV.B
MOV.W
MOV.L
Example of Conventional CPU
CMP.W
BGE
BLT
SUB.W
BEQ
Rev. 2.00, 09/04, page 21 of 720
#H'12,R0
#H'1234,R0
#H'12345678,R0
R1,R0
TRGET0
TRGET1
#1,R0
TRGET