HD64F7047FW40V Renesas Electronics America, HD64F7047FW40V Datasheet - Page 157

• Manufacturer Part Number: HD64F7047FW40V
• Description: MCU 5V 256K I-TEMP,PB-FREE 100-Q
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047FW40V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

8.2.7
DTER which is comprised of seven registers, DTEA to DTEF, is a register that specifies DTC
activation interrupt sources. The correspondence between interrupt sources and DTE bits is shown
in table 8.1.
Note:
Bit
7
6
5
4
3
2
1
0
*
Bit Name
DTE*7
DTE*6
DTE*5
DTE*4
DTE*3
DTE*2
DTE*1
DTE*0
DTC Enable Registers (DTER)
The last character of the DTC enable register’s name comes here.
Example: DTEB3 in DTEB, etc.
Initial
Value
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
DTC Activation Enable 7 to 0
Setting this bit to 1 specifies the corresponding interrupt
source to a DTC activation source.
[Clearing conditions]
•
•
•
These bits are not cleared when the DISEL bit is 0 and
the specified number of transfers have not ended.
[Setting condition]
1 is written to the bit to be set after a 0 has been read
from the bit
When the DISEL bit is 1 and the data transfer has
ended
When the specified number of transfers have ended
0 is written to the bit to be cleared after 1 has been
read from the bit
Rev. 2.00, 09/04, page 115 of 720