HD64F7047FW40V Renesas Electronics America, HD64F7047FW40V Datasheet - Page 657

• Manufacturer Part Number: HD64F7047FW40V
• Description: MCU 5V 256K I-TEMP,PB-FREE 100-Q
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047FW40V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

In this example, the HSTBY pin is driven low, then the transition to hardware standby mode is
made. Hardware standby mode is cleared when the HSTBY pin is driven high and then the RES
pin is driven high after the elapse of the oscillation stabilization time of the clock pulse.
24.3.4
Module standby mode can be set for individual on-chip peripheral functions.
When the corresponding MSTP bit in MSTCR is set to 1, module operation stops at the end of the
bus cycle and a transition is made to module standby mode. The CPU continues operating
independently.
When the corresponding MSTP bit is cleared to 0, module standby mode is cleared and the
module starts operating at the end of the bus cycle. In module standby mode, the internal states of
modules are initialized.
After reset clearing, the SCI, MTU, MMT, CMT, and A/D converter are in module standby mode.
When an on-chip supporting module is in module standby mode, read/write access to its registers
is disabled.
24.4
24.4.1
When a transition is mode to software standby mode while the port high-impedance bit (HIZ) in
SBYCR is 0, I/O port states are retained. Therefore, there is no reduction in current consumption
for the output current when a high-level signal is output.
Oscillator
RES
HSTBY
Module Standby Mode
Usage Notes
I/O Port Status
Figure 24.3 Transition Timing to Hardware Standby Mode
Rev. 2.00, 09/04, page 615 of 720
stabilization
Oscillation
time
Reset
exception
handling