HD64F7047FW40V Renesas Electronics America, HD64F7047FW40V Datasheet - Page 187

• Manufacturer Part Number: HD64F7047FW40V
• Description: MCU 5V 256K I-TEMP,PB-FREE 100-Q
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047FW40V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

9.7
When a read from a slow device is completed, data buffers may not go off in time, causing conflict
with the next access data. If there is a data conflict during memory access, the problem can be
solved by inserting a wait in the access cycle.
To enable detection of bus cycle starts, waits can be inserted between access cycles during
continuous accesses of the same CS0 space by negating the CS0 signal once.
9.7.1
Waits are inserted so that the number of write cycles after read cycle and the number of cycles
specified by IW01 or IW00 bits of BCR can be inserted. When idle cycles already exist between
access cycles, only the number of empty cycles remaining beyond the specified number of idle
cycles are inserted.
9.7.2
For consecutive accesses to the same CS0 space, waits are inserted to provide the number of idle
cycles designated by bit CW0 in BCR2. However, in the case of a write cycle after a read, the
number of idle cycles inserted will be the larger of the two values designated by the IW and CW
bits. When idle cycles already exist between access cycles, waits are not inserted.
Figure 9.7 shows an example. A continuous access idle is specified for CS0 space, and CS0 space
is consecutively write-accessed.
Figure 9.7 Example of Idle Cycle Insertion at Same Space Consecutive Access
Waits between Access Cycles
Prevention of Data Bus Conflicts
Simplification of Bus Cycle Start Detection
Address
WRL
Data
CS0
RD
CK
CS0 space access
T1
T2
Idle cycle
Tidle
CS0 space access
T1
Rev. 2.00, 09/04, page 145 of 720
T2