HD64F7047FW40V Renesas Electronics America, HD64F7047FW40V Datasheet - Page 639

• Manufacturer Part Number: HD64F7047FW40V
• Description: MCU 5V 256K I-TEMP,PB-FREE 100-Q
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047FW40V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Pin Functions in RAM Monitor Mode
23.3
23.3.1
In this mode, the branch destination address is output when a branch occurs in the user program.
Branches may be caused by branch instruction execution or interrupt/exception processing, but no
distinction is made between the two in this mode.
23.3.2
Operation starts in branch trace mode when AUDRST is asserted, AUDMD is driven low, then
AUDRST is negated.
Figure 23.2 shows an example of data output.
While the user program is being executed without branches, the AUDATA pins constantly output
0011 in synchronization with AUDCK.
When a branch occurs, after execution starts at the branch destination address in the PC, the
previous fully output address (i.e. for which output was not interrupted by the occurrence of
another branch) is compared with the current branch address, and depending on the result,
AUDSYNC is asserted and the branch destination address is output after 1-clock output of 1000
(in the case of 4-bit output), 1001 (8-bit output), 1010 (16-bit output), or 1011 (32-bit output) from
the AUDATA pins. The initial value of the compared address is H'00000000.
On completion of the cycle in which the address is output, AUDSYNC is negated and 0011 is
simultaneously output from the AUDATA pins.
If another branch occurs during branch destination address output, the later branch has priority for
output. In this case, AUDSYNC is negated and the AUDATA pins output the address after
outputting 10xx again (figure 23.3 shows an example of the output when consecutive branches
Pin
AUDCK
AUDSYNC
AUDATA3 to
AUDATA0
Branch Trace Mode
Overview
Operation
Description
The external clock input pin. Input the clock to be used for debugging to this
pin. The input frequency must not exceed 1/4 the operating frequency.
Do not assert this pin until a command is input to AUDATA externally and the
necessary data can be prepared. For details, see the protocol description in
the following.
When a command is input externally, data is output after Ready transmit.
Output starts when AUDSYNC is negated. For details, see the protocol
description in the following.
Rev. 2.00, 09/04, page 597 of 720