HD64F7047FW40V Renesas Electronics America, HD64F7047FW40V Datasheet - Page 23

• Manufacturer Part Number: HD64F7047FW40V
• Description: MCU 5V 256K I-TEMP,PB-FREE 100-Q
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047FW40V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 22 High-Performance User Debugging Interface (H-UDI) .................581
22.1 Overview........................................................................................................................... 581
22.2 Input/Output Pins .............................................................................................................. 583
22.3 Register Description.......................................................................................................... 583
22.4 Operation .......................................................................................................................... 587
22.5 Usage Notes ...................................................................................................................... 590
Section 23 Advanced User Debugger (AUD)....................................................593
23.1 Overview........................................................................................................................... 593
23.2 Pin Configuration.............................................................................................................. 594
23.3 Branch Trace Mode........................................................................................................... 597
23.4 RAM Monitor Mode ......................................................................................................... 598
23.5 Usage Notes ...................................................................................................................... 601
Section 24 Power-Down Modes ........................................................................603
24.1
24.2 Register Descriptions ........................................................................................................ 606
24.3 Operation .......................................................................................................................... 611
22.1.1 Features................................................................................................................ 581
22.1.2 Block Diagram..................................................................................................... 582
22.3.1 Instruction Register (SDIR) ................................................................................. 584
22.3.2 Status Register (SDSR)........................................................................................ 585
22.3.3 Data Register (SDDR) ......................................................................................... 586
22.3.4 Bypass Register (SDBPR) ................................................................................... 586
22.4.1 H-UDI Interrupt ................................................................................................... 587
22.4.2 Bypass Mode ....................................................................................................... 590
22.4.3 H-UDI Reset ........................................................................................................ 590
23.1.1 Features................................................................................................................ 593
23.1.2 Block Diagram..................................................................................................... 594
23.2.1 Pin Descriptions................................................................................................... 595
23.3.1 Overview.............................................................................................................. 597
23.3.2 Operation ............................................................................................................. 597
23.4.1 Overview.............................................................................................................. 598
23.4.2 Communication Protocol ..................................................................................... 599
23.4.3 Operation ............................................................................................................. 599
23.5.1 Initialization ......................................................................................................... 601
23.5.2 Operation in Software Standby Mode.................................................................. 601
23.5.3 Setting the PA15/CK/POE6/TRST/BACK pin.................................................... 601
23.5.4 Pin States ............................................................................................................. 601
23.5.5 AUD Activation Procedures ................................................................................ 602
24.2.1 Standby Control Register (SBYCR) .................................................................... 607
24.2.2 System Control Register (SYSCR) ...................................................................... 608
24.2.3 Module Standby Control Register 1 and 2 (MSTCR1 and MSTCR2)................. 609
Input/Output Pins ............................................................................................................. 606
Rev. 2.00, 09/04, page xxi of xl