hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 93

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

The Command Stack address range is bounded by the values in Address List Words 0 and 2. The Data Stack address
range is bounded by the values in Address List Words 4 and 6. The “Next Address” Words 1 and 5 must be initialized
by the host for the first data written after reset; thereafter these values are maintained by the device each time a new
MIL-STD-1553 message is recorded.
Two optional stack address interrupts are offered. When enabled, a Command or Data Stack Address Interrupt occurs
whenever the matching RAM address in the Stack is written. The Address List contains the address values for these
optional “stack utilization” interrupts.
For SMT mode, the 8-word Monitor Address List is defined in Table 10.
Message
Word
Block
Word 2
Word 1
Word 0
Message
Word
Block
Word 7
Word 6
Word 5
Word 4
Word 3
Word Name Word Function when using 16-bit time tag
Message
Time Stamp
Bits 47 ~ 32
Message
Time Stamp
Bits 31 ~ 16
Message
Time Stamp
Bits 15 ~ 0
Word Name Word Function when using 16-bit time tag
Data Stack
Interrupt
Address
Data Stack
End Address
Data
Stack Next
Address
Data
Stack Start
Address
Command
Stack
Interrupt
Address
Upper 16-bit word of message 48-bit time stamp.
Middle 16-bit word of message 48-bit time stamp.
Lower 16-bit word of message 48-bit time stamp.
Word 0 is the first word in the Command Stack entry for each message.
Host initialized with a RAM address value if this interrupt is enabled.
If enabled, an interrupt occurs when the matching RAM address is written. Address
must occur within the range bounded by Words 4 and 6.
Host initialized, defines SMT Data Stack upper address boundary.
Must be host initialized, usually to match SMT Data Stack Start Address.
Updated by device each time a new MIL-STD-1553 message is recorded.
This value advances through the address range in circular buffer fashion.
Host initialized, defines SMT Data Stack lower address boundary.
Host initialized with a RAM address value if this interrupt is enabled.
If enabled, an interrupt occurs when the matching RAM address is written. Address
must occur within the range bounded by Words 0 and 2.
Table 10. Monitor Address List for SMT Mode
HOLT INTEGRATED CIRCUITS
HI-6130, HI-6131
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