hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 17

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

Pin
BCTRIG
MTRUN
RT1ENA
RT2ENA
RT1LOCK
RT2LOCK
RT1MC8
RT2MC8
RT1SSF
RT2SSF
MTPKRDY
IRQ
ACKIRQ
RT1A4:0
RT1AP
RT2A4:0
RT2AP
Function
Input
50KΩ pull-down
Input
50KΩ pull-down
Inputs
50KΩ pull-down
Inputs
50KΩ pull-down
Outputs
Inputs
50KΩ pull-down
Output
Output
Input
50KΩ pull-down
Inputs
50KΩ pull-ups
Description
BC Trigger input, active high. Used in conjunction with certain BC instructions.
Monitor Run / Stop input, active high. This input starts/stops MT data recording.
Upon going low, the MT stops when the current message is completed.
RT Enable input, active high. This input pin is logically ANDed with the STEX
Start Execution bit in the RT Configuration Register to allow RT operation.
Pin states are latched to the Lock bit in the RTx Operational Status register
when rising edge occurs on the MR pin. If status register Lock bit is high, the
host cannot overwrite the terminal address in the same register. If status register
Lock bit is low, the host can overwrite the terminal address and parity (and the
Lock bit) in the RTx Operational Status register.
Remote Terminal “Reset RT” mode command (MC8) received. This active low
output is asserted at Status Word completion when RT1 or RT2 received a
“Reset Remote Terminal” mode code command. The minimum output pulse
width is 100ns, unaffected by MR assertion.
RT Subsystem Fail input, active high. When this input is high, the selected RT1
or RT2 sets the SUBSYS flag in its transmit status word. This input is logically-
ORed with the same bit in the terminal’s RT1 or RT2 1553 Status Word Bits
register.
Monitor Packet Ready output, active high. This pin is asserted when a message
data packet is complete, as defined by the various MT configuration registers
(maximum word or message count, maximum packet time, etc.) Assertion of
this bit indicates the MT has stopped.
Interrupt request, active low. This pin is asserted each time an enabled interrupt
event occurs. This signal is programmed as a brief low-going pulse output or
as a level output by the INTSEL bit in the Master Configuration Register. If level
output is selected, IRQ stays low until the host acknowledges IRQ by pulsing a
rising edge at the ACKIRQ pin, or by reading the pending interrupt register(s)
containing active interrupt flags.
Interrupt Acknowledge, active high. This input is only used when the INTSEL bit
in Configuration Register 1 is high, enabling level interrupt assertion for the IRQ
pin. When interrupt assertion causes the IRQ pin to go low, a high-going pulse
on ACKIRQ (60ns minimum duration) clears the IRQ output to logic 1. Reading
all non-zero Pending Interrupt registers also clears the IRQ interrupt output.
Remote terminal address bits 4 - 0, and parity bit for RT1 and RT2. The RTAP
pin provides odd parity for the address on pins RTA4:0.
The terminal address and parity pin levels are latched into the respective RT
Operational Status Registers when rising edge occurs on the MR pin. The RT
Operational Status Register value (not these pins) reflects the active terminal
address. The host can overwrite the RT Operational Status register address
value only when the register Lock bit is reset.
HOLT INTEGRATED CIRCUITS
HI-6130, HI-6131
17