hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 129

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

Bit No.
4
3
2
1
0
Mnemonic
MTCRIW
IMTHTD
MTXMF
IMTCKSM
SMT / IMT
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
HOLT INTEGRATED CIRCUITS
Function
IMT Continue Recording After Invalid Word.
When bit 4 equals 0, the IMT stops recording an incomplete message
when an invalid MIL-STD-1553 word is decoded. The invalid word is not
stored, and the IMT awaits word detection per register bits 6-5 before
the next MIL-STD-1553 message is recorded. (default)
When bit 4 equals 1, the MT continues recording an incomplete
message when an invalid MIL-STD-1553 word is decoded. The invalid
word is stored and the IMT continues monitoring the message until
completion or time-out occurs.
IMT (Data Packet) Header and Trailer Disabled.
When bit 3 equals 0, the IMT reserves space for an IRIG-106 packet
header and packet trailer in the RAM stack assigned in the MT Address
List. The Packet Header and Packet Trailer are automatically generated
by the device at packet finalization and stored in the assigned stack.
(default)
When bit 3 equals 1, the IMT generates only the IRIG-106 Packet Body,
stored in the assigned stack. The full stack address range is used for
message storage.
IMT Extended Message Flag Enable.
When register bit 2 equals 0, the recorded status/error flags are limited
to the defined bits in the IRIG-106 Block Status Word. See Section 14.6.
When register bit 2 equals 1, expanded status/error flags are enabled,
occupying “reserved” bit positions in the IRIG-106 Block Status Word.
IMT Checksum Enable
This IMT setting is only meaningful when IMTHTD (register bit 3) equals
0, enabling automatic generation of IRIG-106 data packet header and
packet trailer.
When register bit 1 equals 1, a 16-bit checksum is tallied for the data
packet body, and stored in the packet trailer at packet finalization.
When register bit 1 equals 0, no checksum is tallied for the data packet
body.
Select Simple Monitor Terminal (SMT) or IRIG-106 Monitor Terminal
(IMT).
This register bit must equal logic 0 for IMT operation. When this bit is
zero, the bus monitor operates in IMT IRIG-106 mode with 48-bit time
tag counter resolution.
HI-6130, HI-6131
129