hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 24

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

7. REGISTER & MEMORY
The HI-613x has an internal address space of 32K
16-bit words. Registers occupy the low 80 locations in
this address space. In this data sheet, register / RAM
addresses are expressed as hexadecimal numbers,
using the C programming convention where the prefix
“0x” denotes a hexadecimal value; e.g., 0x00FF
represents 00FF hex.
Figure 2 shows address mapping for registers and
RAM. All registers and some RAM structures have fixed
addresses. Other RAM structures shown are relocatable;
Each relocatable structure has a base address register.
Figure 2 shows the default locations for relocatable
structures. RAM allocations for unused MIL-STD-1553
functions can be reassigned as needed. For example,
an application using just a Bus Monitor can reassign all
BC and RT RAM for monitor needs.
Device RAM and register address mapping is word
oriented, rather than byte oriented. Register and memory
addresses throughout this document reflect word
addressing. For all parallel bus-interface applications
(HI-6130) and most SPI interface applications (HI-
6131), word oriented addressing applies. Word oriented
addressing uses address inputs A15 to A1; address
input A0 is not used. Fifteen bits are sufficient for a 32K
address range.
7.1.
When required by the application, parallel bus
interface HI-6130 devices can use byte transfers. All
8-bit microprocessors (and some 16-bit and 32-bit
microprocessors) use (or can use) byte-oriented memory
accesses. To provide byte capability, the HI-6130 uses
the sixteenth bus address input, A0. Thus 16 address
pins A15:0 address 64K bytes. The A0 input denotes
whether the first or second byte in the word is being
addressed, while A15-A1 indicate the word address. This
difference must be considered when assigning HI-6130
pointer values or accessing RAM or registers. From the
microprocessor’s standpoint, any host-assigned RAM
buffer address will be double the value of the buffer’s
pointer stored in RAM. This paragraph only applies to
HI-6130 using 8-bit bus width. From this point on, all
register and memory addresses presented in this data
sheet are 15-bit word addresses.
From the host standpoint, register operations and RAM
operations are performed identically. Depending on
function, individual registers may be read-only, read-
write, or a combination of read-only and read-write bit
ADDRESSING
8-bit Bus Operation: (HI-6130 Only)
HOLT INTEGRATED CIRCUITS
HI-6130, HI-6131
24
fields. Read-only registers and read-only register bit
fields, are protected against accidental host overwrite
by device logic.
Addresses in the range 0x004C to 0x7FFF apply to
static RAM memory. All RAM is read-write and can be
written or read by either the host or the internal device
logic. Both host and the device update certain RAM
locations (e.g., RT Descriptor Table Control Words).
These locations are protected against accidental data
collision by arbitration logic which acts when concurrent
writes by both host and device occur.
8. REGISTER DEFINITIONS
Residing at the start of the memory address space, 80
addresses are reserved for HI-613x registers. Register
addresses overlay the shared RAM address space.
Register bits are active high and bit 15 is the most
significant.
Table 4 lists all device registers.