hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 176

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

19.5.4. Receive Mode Control Word
Receive Mode Control Words apply when the command word T/R bit equals zero (receive) and the subaddress field
has a value of 0 or 31 (0x1F). The descriptor Control Word defines terminal command response and interrupt behavior,
and conveys activity status to the host. It is initialized by the host before terminal execution begins. Bits 8-11 cannot be
written by the host; these bits are updated by the device during terminal execution, that is, when Configuration Register
1 STEX bit equals 1. The host can write bit 2 only when STEX equals zero; bits 3 and 12-15 can be written anytime.
This register is cleared to 0x0000 by MR master reset. Software reset (SRST) clears just the DBAC, DPB and BCAST
bits. Following any read cycle to the Control Word address, the DBAC bit is reset.
When single-message indexed buffering or ping-pong buffering is used instead of SMCP (Simplified Mode Code Pro-
cessing), the receive mode Control Word looks like this:
When SMCP applies, the number of active mode Control Word bits is reduced:
NOTE: ‘Reset’ refers to bit value following Master Reset (MR). The bit value following software reset is un-
changed unless specifically indicated by an “SR” value.
Bit No. Mnemonic R/W
MSB
MSB
15
14
15 14 13 12 11 10 9
15 14 13 12 11 10 9
H
H
IXEQZ
IWA
H
H
H
H
H
H
D1
D1
D
X
D
D
Reset
D
D
8
8
0
0
X
7
X
7
X
X
6
6
Function
Interrupt When Index Equals Zero.
If the Interrupt Enable Register IXEQZ bit is high, assertion of this bit enables
generation of an interrupt for mode code commands using indexed buffer
mode when the INDX value decrements from 1 to 0. Upon completion of
command processing that results in INDX = 0, when IXEQZ interrupts are
enabled, an IXEQZ interrupt is entered in the Pending Interrupt Register, the
INTMES output pin is asserted, and the interrupt is registered in the Interrupt
Log.
Interrupt When Accessed.
If the Interrupt Enable Register IWA bit is high, assertion of this bit enables
interrupt generation at each instance of a valid mode code command. Upon
completion of command processing, when IWA interrupts are enabled, an
IWA interrupt is entered in the Pending Interrupt Register, the INTMES output
pin is asserted, and the interrupt is registered in the Interrupt Log.
X
X
5
5
HOLT INTEGRATED CIRCUITS
X
X
4
4
HI-6130, HI-6131
H
X
3
3
H
X
2
2
X
X
1
1
X
X
0
0
176
LSB
LSB
D1
D1
H
D
H
D
X
X
Bit maintained by host
Bit maintained by device
Bit set by device, reset by host read cycle
Bit is not used, may be logic 0 or 1
Bit maintained by host
Bit maintained by device
Bit set by device, reset by host read cycle
Bit is not used, may be logic 0 or 1