hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 184

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

The following bits comprise the receive subaddress Message Information Word:
MSB
Bit No.
15
14
13
12
10
11
9
8
15 14 13 12 11 10 9
Mnemonic
TMOERR
IWDERR
GAPERR
WCTERR
SYNERR
MERR
WASBSY
ILCMD
Function
Time-Out Error.
This bit is asserted for RT-RT receive messages when the transmitting terminal fails to
start its status word and data transmission before time-out occurs, per TOSEL0-1 bits in
Configuration Register 2.
Invalid Word Error.
Assertion of this bit indicates Manchester error or parity error was observed in a received
data word.
Gap Error.
Assertion of this bit indicates bus activity was detected immediately after the last expected
receive data word or that a gap occurred before all expected data words were received.
Word Count Error.
This bit is asserted if command is received with less data words than the command word
specifies. For example, a receive command for three data words is received with two
contiguous data words.
Sync Error.
This bit is asserted when an incorrect (command/status) sync type occurs in received data
words.
Message Error.
This bit is asserted when message error status change occurs during command process-
ing. See bits 7 and 11-15 for details.
Was Busy.
This bit is asserted when the terminal responds to the receive command with BUSY
status, due to global BUSY bit set in 1553 Status Bits Register, or command-specific
MKBUSY bit set in the descriptor table Control Word. Received data words were buffered
normally.
Illegal Command Received.
This bit is asserted when the Illegalization Table bit corresponding to the received com-
mand is logic 1. The Illegalization Table should only contain nonzero values when “illegal
command detection” is being applied. See Section 19.2 for further information.
8
7
6
5
HOLT INTEGRATED CIRCUITS
4
HI-6130, HI-6131
3
2
1
0
184
LSB