hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 168

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

19.5. Descriptor Table
The Descriptor Table, resides in shared RAM, in ad-
dress range 0x0200 to 0x03FF. This table is initialized
by the host (or auto-initialization) to define how the ter-
minal processes valid commands. Descriptor Table set-
tings for each command specify where message data is
stored, how data is stored, whether host interrupts are
generated, and other aspects essential to command pro-
cessing. Shown in Figure 16, the table consists of 128
consecutive “descriptor blocks”, each comprised of four
16-bit words. The table is organized into four quadrants.
The Receive Subaddress and Transmit Subaddress
quadrants define response for commands having a sub-
address field ranging from 1 to 30 (0x1E). These are
simple N-data word receive or transmit commands,
where N can range from 1 to 32 words. When the com-
mand T/R bit equals 0, the receive command quadrant
applies. When the T/R bit equals 1, the transmit com-
mand quadrant applies.
Both subaddress quadrants are padded at top and bot-
tom with unused Descriptor Blocks for subaddresses 0
and 31 (0x1F). The word space reserved for SA0 and
SA31 aligns the table addressing, but values stored in
these eight locations is not used. Command subaddress-
es 0 and 31 indicate mode commands. The response
for commands containing either SA value is defined in
the two mode command table quadrants. The Receive
Mode Command quadrant applies when the command
word T/R bit equals 0, while the Transmit Mode Com-
mand quadrants applies when T/R equals 1.
The term “Transmit Mode Command” is a misnomer.
All defined mode commands with mode code less than
0x0F haveT/R bit equal to 1, yet none of these mode
commands transmits a data word. They transmit only
the terminal status word, just like receive commands.
Within the Receive and Transmit Mode Command
quadrants, block addressing is based on the low order
5 bits in the command word, containing the mode code
value. This is fundamentally different from the Subad-
dress quadrants in which block addressing is based on
the 5-bit subaddress field. Figure 17 shows how to de-
rive Control Word address from the received Command
Word. The Control Word address for the last valid com-
mand can also be found in the Current Control Word
Address register.
All 128 4-word Descriptor Blocks start with a Control
Word. There are four Control Word variants (described
later), based on command type: receive vs. transmit and
mode vs. non-mode commands. All descriptor Control
Words are initialized by the host (or auto-initialization)
HOLT INTEGRATED CIRCUITS
HI-6130, HI-6131
168
to define basic command response. Each Control Word
specifies the data buffer method and host interrupt for a
specific subaddress or mode command.
Each subaddress has both a Receive Subaddress block
and a Transmit Subaddress block. Receive and transmit
commands to the same subaddress can be programmed
to respond differently.
The function of the three remaining descriptor words (in
each 4-word block) depends on the data buffer method
specified in the Control Word. There are 4 data buffer
options available:
Indexed (or Single Buffer) Method where a predeter-
mined number of messages is transacted using a single
data buffer in shared RAM. Several host interrupt op-
tions are offered, including an interrupt generated when
all N messages are successfully completed.
Double (or Ping-Pong) Buffer Method where succes-
sive messages alternate between two data buffers in
shared RAM. Several host interrupt options are offered.
Circular Buffer Mode 1 where buffer boundaries deter-
mine when the bulk transfer is complete and message
information and time-tag words are stored with message
data in a common buffer. Several host interrupt options
are offered, including an interrupt generated when the
allocated data buffer is full.
Circular Buffer Mode 2 where the number of messages
transacted defines bulk transfer progress, and message
data words are stored contiguously in one buffer while
message information and time-tag words are stored in
a separate buffer. Several host interrupt options are of-
fered, including an interrupt generated when all N mes-
sages are successfully completed.
The 4-word Descriptor Table entry for each command
(its descriptor block) begins with a Control Word. There
are four types of descriptor Control Word:
The descriptor Control Word is initialized by the host to
select data buffer method and interrupt options. After
a command is processed by the HI-6130/21 terminal,
the device updates the command’s descriptor Control
Word. Update will differ based on the chosen data buf-
fer method. Reading the descriptor table can differ from
other RAM accesses. For HI-6130, see Section XX. For
HI-6131, see Sections XX and XX.
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Receive Subaddress Control Word
Transmit Subaddress Control Word
Receive Mode Command Control Word
Transmit Mode Command Control Word