hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 202

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

Increasing
Memory
Address
Buffer Start
Buffer End
Address
Address
Unlike Indexed mode, Data Block completion is based on Buffer Full / Buffer Empty, not number of messages.
Buffer size was purposely sized to yield remaining capacity after 2 full-count messages, to illustrate device behavior.
The circular buffer should have a 33-word pad beyond its End Address to deal with buffer overrun without data loss.
Figure 23. Circular Buffer Mode 1 Example for a Receive Subaddress
Receive Subaddress
Msg Info Word 3
Time-Tag Word 3
Descriptor Block
Data Words 2-31
Data Words 2-31
Data Words 2-31
Msg Info Word 2
Msg Info Word 1
Current Address
Time-Tag Word 2
Time-Tag Word 1
Data Word 32
Data Word 32
Data Word 32
Start Address
Control Word
End Address
Data Word 1
Data Word 1
Data Word 1
for a
HOLT INTEGRATED CIRCUITS
0x0565
0x0547 - 0x0564
0x0546
0x0545
0x0544
0x0543
0x0525 - 0x0542
0x0524
0x0523
0x0522
0x0521
0x0503 - 0x0520
0x0502
0x0501
0x0500
RAM
Address
End Address = 0x0545 Buffer end address in RAM
Current Address = 0x0500 Buffer current address in RAM
Start Address = 0x0500 Buffer start address in RAM
Control Word = 0x8001 Circular Mode 1, IXEQZ Interrupt
Initialized Descriptor Values
HI-6130, HI-6131
202
Unless serviced by host
after Message #3 Interrupt,
Message #4 will overwrite
buffer, starting at 0x0500
(1 + Data Word 32 address) ≥ End Address.
Device updates Current Address to
equal the Start Address, 0x0500.
IXEQZ interrupt is generated.
(1 + Data Word 32 address) < End Address.
Device updates Current Address to 0x0544.
(1 + Data Word 32 address) < End Address.
Device updates Current Address to 0x0522.
Receive Message #3
32 Data Words
Receive Message #3
32 Data Words
Receive Message #3
32 Data Words