hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 220

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

Note: Soft reset for the Bus Monitor re-initializes the stack address pointers, but does not clear the allocated buffer
space in the stack(s).
The Bus Monitor automatically starts (MTENA is set in register 0x0000) after soft reset completion, if the following
requirements are met. Message recording commences when a new valid command is received:
To manually start the Bus Monitor after soft reset completion (indicated by READY signal assertion), the host must
set MTENA bit 12 in register 0x0000, if auto-start was disabled or otherwise failed for one or more of these reasons:
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The MTENA pin is logic 1 during the soft reset event
The MTENA pin was logic 1 in the Master Configuration Register when EECOPY created the EEPROM image.
The MTENA bit 12 is logic 1 in the EEPROM Master Configuration Register image because EECOPY used these
unlock codes during EEPROM programming: Unlock Word 1 = 1010-XX11-XXXX-1010 and Unlock Word 2 =
0101-XX00-XXXX-0101 where X denotes “don’t care”.
The MTENA pin was logic 0 during the soft reset event
The MTENA pin was logic 0 in the Master Configuration Register when EECOPY created the EEPROM image.
A new EEPROM image is needed to allow auto-start after MT soft reset.
The MTENA bit 12 is logic 0 in the EEPROM Master Configuration Register image because the unlock codes
used by EECOPY were wrong. A new EEPROM image is needed to allow auto-start after Bus Monitor soft reset.
HOLT INTEGRATED CIRCUITS
HI-6130, HI-6131
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