hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 216

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

The overall checksum includes individual terminal checksums for RT1, RT2 and Bus Monitor, which the EECOPY
process stored at EEPROM locations corresponding to RAM addresses 0x01C0, 0x01E0 and 0x005C respectively. All
checksums stored by the EECOPY process use two’s complement format. Each checksum is calculated by summing
the individual 16-bit data values (ignoring carry) over the full set of included register and RAM addresses. The summa-
tion is then complemented, then incremented (ignoring carry) to yield the stored two’s complement checksum value.
When the device performs checksum-based error checking, a new summation is tallied (ignoring carry) for the indi-
vidual 16-bit data values over the range of included register and RAM addresses. When this summation is added to
the previously stored two’s complement checksum, the result is zero when the new data summation is the same as
that tallied by EECOPY when the checksum was stored.
The registers tallied in each of the RT1, RT2 and SMT or IMT terminal checksums are summarized on the next pages.
These individual checksums are used for error checking during soft reset events. Soft reset occurs for RT1, RT2 or
SMT / IMT when RT1RESET bit 10, RT2RESET bit 11 and/or MTRESET bit 12 is set in the Master Status and Reset
Register 0x0001. One, two or three terminal reset bits can be individually or simultaneously set, without affecting other
on-chip terminals or the Bus Controller. The HI-613x Bus Controller does not have soft reset.
Address
0x000C
0x000D
0x003C
0x000B
0x000E
0x001E
0x003A
0x003B
0x004B
0x0018
0x0021
0x0027
0x0030
0x0031
0x0035
0x0036
0x0037
0x0043
0x0044
0x0049
HOLT INTEGRATED CIRCUITS
HI-6130, HI-6131
BC Message Time Remaining Register
BC Frame Time Remaining Register
RT1 Operational Status Register
RT2 Operational Status Register
RT1 Built-In Test Word Register
RT2 Built-In Test Word Register
RT1 Memory Address Pointer
RT2 Memory Address Pointer
MT Memory Address Pointer
BC Memory Address Pointer
BC Condition Code Register
MT Current Address Pointer
MT Time Tag Counter High
BC Time Tag Counter High
MT Time Tag Counter Low
BC Time Tag Counter Low
MT Time Tag Counter Mid
216
Excluded Register Name
MT Last Address Pointer
RT1 Time Tag Counter
RT2 Time Tag Counter