hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 91

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

12. SIMPLE MONITOR TERMINAL (SMT)
The HI-613x can operate as an autonomous MIL-STD-1553 Bus Monitor, requiring minimal host support. Two
fundamentally different monitor modes are offered. Each of these modes has a separate data sheet section describing
registers used and operational details. Information regarding the alternative IRIG-106 Monitor Terminal (IMT) begins
in Section 14.
12.1. Overview
Simple Monitor Terminal (SMT) Mode has its own dedicated Time Tag counter, and can use either a 16- or 48-bit
Time Tag scheme. The SMT monitor utilizes two stacks in RAM: a Command Stack and a Data Stack. Each recorded
MIL-STD-1553 message appends a fixed length entry into the Command Stack and a variable length entry into the
Data Stack.
The SMT message records a fixed length “message block” In the Command Stack for each MIL-STD-1553 message.
The advantage of fixed length Command Stack message blocks is that the host can quickly jump to the block start
address for any message.
The number of words added to the Data Stack for each message depends on the MIL-STD-1553 message type,
ranging from zero (broadcast mode command without data) to 35 words (for a 32 data word RT-RT command).
In SMT mode, both stacks are fully utilized for recording message data. Unlike IMT mode, there is no option for
generating a data header or data trailer. SMT monitor mode allows selective monitoring of MIL-STD-1553 messages,
based on the address, subaddress and T/R status in each monitored Command Word, or can monitor all messages,
when preferred. The SMT monitor offers flexible interrupt options.
In Master Configuration Register 0x0000, MTENA bit 8 is logically ANDed with the MTENA input pin to enable the SMT
monitor. If the MTENA input pin or Master Configuration Register bit 8 equals logic 0, Bus Monitor operation is disabled.
When the pin and Master Configuration Register MTENA bit 8 are both logic 1, the Bus Monitor is enabled. Operation
commences when the receiver first decodes MIL-STD-1553 activity meeting the “start record” criteria selected by bits
6-5 in the MT Configuration Register 0x0029. If monitor operation is underway when Master Configuration Register
MTENA bit 8 or MTENA input pin becomes logic 0, monitor operation stops after completion of any message already
underway.
The HI-613x is configured for SMT operation by writing bits 1-0 in the MT Configuration Register 0x0029.
When MT Configuration Register bits 1-0 equal 11, the SMT operates with 16-bit Time Tag resolution and each recorded
MIL-STD-1553 message adds a four word entry in the Command Stack. This is summarized in Table 8.
Message
Word
Block
Word 3
Word 2
Table 8. Command Stack Message Block for SMT Monitor using 16-bit Time Tag
Word Name Word Function when using 16-bit time tag
Message
Command
Word
Data Block
Pointer
Message Command Word.
The MIL-STD-1553 Command Word that initiated the message.
For an RT-RT message, Receive Command Word 1 is stored here; Transmit Command
Word 2 is the first stored word in the Message Data Block.
Starting address in the Data Stack for the corresponding message data block.
HOLT INTEGRATED CIRCUITS
HI-6130, HI-6131
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