hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 201

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

Memory Address for the Applicable
Subaddress Block is Derived From
the Decoded Command Word
Descriptor block is initialized so Current Address equals buffer Start Address. After each successful
message transaction, Current Address is adjusted to point past last data word accessed. If adjusted
Current Address points past End Address, the Current Address is reinitialized to match Start Address
and an optional interrupt is generated to notify host that the pre-determined data block
was fully transacted.
Figure 22. Illustration of Circular Buffer Mode 1
Descriptor Block
HOLT INTEGRATED CIRCUITS
for Subaddress
Current Address
Start Address
Control Word
End Address
Increasing
HI-6130, HI-6131
Memory
Address
201
FirstMessage
in Data Block
Last Message
in Data Block
Current
Message
Message Info Word
Message Info Word
Message Info Word
More Messages
More Messages
Circular Buffer
Time-Tag Word
Time-Tag Word
Time-Tag Word
Data Word(s)
Data Word(s)
Data Word(s)
in Data Block
Data Word N
Subaddress
Data Word N
Data Word N
in Data Block
Data Word 1
Data Word 1
Data Word 1
Assigned
End
Address
Current
Address
Start
Address