hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 20

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

Pin
WAIT / WAIT
CE
SO
SI
SCK
Pin
Function
Output
Input
50KΩ pull-up
Output
Input
50KΩ pull-down
Input
50KΩ pull-down
Table 3. Pins that apply to HI-6131 only (Host SPI bus interface)
Function
Description
Host bus read cycle WAIT or WAIT output. The HI-6130 WPOL input pin sets the
active level for this “wait” output.
Read cycles are slower than write cycles, but prefetching speeds data availability
for multi-word sequential address read cycles. For every new bus read cycle,
the HI-6130 asserts WAIT. Connected to the processor WAIT or WAIT input, this
action inserts one or more processor wait states (depending on processor clock
frequency) while the HI-6130 fetches the first word. After reading each HI-6130
register or RAM address, the device prefetches and retains data from the next
address. If the next bus access reads that sequential address, the data is ready
without WAIT assertion, even if that read cycle occurs some time later. While
the prefetch “chain” is broken by any write cycle, each read cycle prefetches
and retains data from the next address, whether or not it is needed. Thus WAIT
assertion only occurs for the first word read.
The WAIT output is useful when the host processor runs at high clock rates and/
or when processor read wait states do not provide adequate timing margin for
worst case (slowest) read cycle timing for the HI-6130. Using the WAIT output
for the slow, first read cycle means the processor bus interface can be optimized
to use faster no-wait cycles for write operations, and for reading words 2 through
N in successive address, N-word read operations. Processors lacking a WAIT
or WAIT input pin are typically configured to insert a fixed number of wait states
for every read/write cycle.
Description
Chip Enable, active low. When asserted, this pin enables host read or write
accesses to device RAM or registers via host SPI port. The HI-6131 SPI port
operates in Slave mode. This pin is connected to the Slave Select output on
the host SPI port.
Serial Peripheral Interface (SPI) Serial Output pin. This pin is connected to
MISO (Master In - Slave Out) pin on host SPI port. The SO pin is tri-stated
when not transmitting serial data to the host.
Serial Peripheral Interface (SPI) Serial Input pin. This pin is connected to
MOSI (Master Out - Slave In) pin on host SPI port.
Serial Peripheral Interface (SPI) Serial Clock pin. This pin is connected to SCK
output pin on host SPI port.
HOLT INTEGRATED CIRCUITS
HI-6130, HI-6131
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