hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 90

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

Bit No.
8 − 5
2 − 0
2 − 1
9
4
3
0
For the BC Interrupt Enable Register and the BC Interrupt Output Enable Register only
Mnemonic
STATSET
BCIRQ3:0
BCMERR
BCEOM
Reserved
Reserved
BCIP
Function
BC Status Set Interrupt.
The BC received an RT Status Word containing the wrong RT address field, or having
an unexpected bit value for at least one of the eight non-reserved status bits. The
expected value for these bits (excluding the BCR bit) is usually 0.
The BCR (broadcast command received) bit can have an expected value of 1 when
BCR Mask Enable bit in the BC Configuration Register is logic 0. In this case, the
Mask Broadcast bit in the message block Control Word shows the expected value
of the Status Word BCR bit. If the Control Word’s Mask Broadcast bit is logic 1, the
expected value of BCR in the RT Status Word is logic 1.
BC Interrupt Request Bits 3-0.
When this 4-bit field is nonzero, the BC executed an IRQ op code. The value of bits 8:5
will equal the value of the 4 LSBs in the parameter associated with the IRQ op code.
The user may define the 4- bit pattern to suit application requirements.
BC Message Error Interrupt.
A non-broadcast message ended with RT Status Word containing the ME Message
Error status bit set.
BC End of Message Interrupt.
The successful completion of a message, regardless of validity.
Bits 2-0 cannot be written, and read back 000.
Bits 2-1 cannot be written, and read back 00.
BC Interrupt Pending.
This bit is set when one or more additional bits are set in the bit range 15-3.
HOLT INTEGRATED CIRCUITS
HI-6130, HI-6131
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