hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 35

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

9.3.
Thirteen HI-613x registers are used for host interrupt management. There are four 3-register groups, separated by
function. One register triplet is used for Hardware interrupts, plus one register triplet each for Bus Controller, Bus
Monitor and Remote Terminal interrupts. Each group (BC, MT, RT, Hardware) has
•
•
•
Bit No.
3
2
1
0
An Interrupt Enable Register to enable and disable interrupts
A Pending Interrupt Register to capture the occurrence of enabled interrupts
An Interrupt Output Enable Register to also enable IRQ output to the host, for interrupts enabled in the Interrupt
Enable Register
Hardware Interrupt Registers and the Interrupt Log Buffer
Mnemonic
RT2INH
RT1INH
EECKE
RAMIF
R/W
R
R
R
R
Reset
0
0
0
0
HOLT INTEGRATED CIRCUITS
Function
Remote Terminal 2 Bus Inhibited.
This bit is high when one bus is inhibited for RT2 due to execution of a
“bus shutdown” mode code command. The shut-down bus is identified
in the RT2 BIT (built-in test) Word Register. Shut-down can be ended
by “bus shutdown override” mode code command, MR reset or setting
the RT2RESET bit in this register.
Remote Terminal 1 Bus Inhibited.
This bit is high when one bus is inhibited for RT1 due to execution of a
“bus shutdown” mode code command. The shut-down bus is identified
in the RT1 BIT (built-in test) Word Register. Shut-down can be ended
by “bus shutdown override” mode code command, MR reset or setting
the RT1RESET bit in this register.
EEPROM Checksum Error.
This function only applies when the AUTOEN input pin is logic 1 at
rising edge of MR Master Reset. This enables auto-initialization from
serial EEPROM, as well as RT or MT soft reset with auto-initialization.
The EECKE bit is set (as well as bit 14 in the Hardware Pending
Interrupt Register, 0x0006) when a serial EEPROM checksum failure
occurs. Such failure may occur during full auto-initialization after MR
master reset, or during execution of a partial, terminal-specific reset
after assertion of the RT1RESET, RT2RESET or MTRESET bits in this
register.
RAM Initialization Fail Interrupt.
This function only applies when the AUTOEN input pin is logic 1 at
rising edge of MR Master Reset. This enables auto-initialization from
serial EEPROM, as well as terminal-specific partial auto-initialization
during RT or MT soft reset.
The RAMIF bit is set (as well as bit 13 in the Hardware Pending
Interrupt Register, 0x0006) when one or more initialized RAM locations
do not match their two corresponding serial EEPROM byte locations.
Such failure may occur during full auto-initialization after MR master
reset, or during execution of a partial, terminal-specific reset after
assertion of the RT1RESET, RT2RESET or MTRESET bits in this
register.
HI-6130, HI-6131
35