hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 80

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

11.2. Start Address Register for Bus Controller (BC) Instruction List (0x0033)
This 16-bit register is Read-Write and is fully maintained by the host. This register is cleared after MR pin master reset.
This register is initialized with the base address of the re-locatable BC Instruction List in device RAM.
11.3. Bus Controller (BC) Instruction List Pointer (0x0034)
This 16-bit register is Read-Only and is fully maintained by the device. When the bus controller is enabled, setting
BCSTRT bit 13 in the Master Configuration Register begins bus controller operation. The device copies the Instruction
List base address from register 0x0033 into this register. This pointer references pairs of words in the BC instruction
list. Each word pair is comprised of an op code word followed by a parameter word. Pointer update occurs just before
execution of the next BC instruction list op code, after execution of the prior op code, and evaluation of its result-
dependent outcome.
MSB
MSB
15 14 13 12 11 10
15 14 13 12 11 10
0
0
Table 7. Effect of “Broadcast Command Received” RT Status Bit on “Status Set” Condition
0
0
0
0
“BCR Mask Enable”
BC Configuration
0
0
Register 0x0032
0
0
bit 0
0
0
0
0
0
0
1
1
1
Register Value
Register Value
0
9
0
9
0
8
0
8
RW
R
7
7
0
0
0
6
0
6
0
0
5
5
Word “Mask BCR”
Message Control
4
4
0
0
0
3
0
3
HOLT INTEGRATED CIRCUITS
bit 5
0
0
1
1
0
0
1
0
0
2
2
HI-6130, HI-6131
0
1
0
1
LSB
LSB
0
0
0
0
MR Reset
Host Access
Bit
MR Reset
Host Access
Bit
80
Received BCR bit
4 in the Remote
Terminal Status
Word
X
0
1
0
1
0
1
Status Word “Status
Resultant Block
Set” bit 11
0
1
1
0
0
1
0