hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 195

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

20.4. Indexed Data Buffer Mode
Also called “single buffer mode”, indexed buffering is
one method for storing message and time-tag informa-
tion and data associated with messages. Buffer mode is
selected for each subaddress or mode code in the De-
scriptor Table Control Words. Indexed mode is enabled
when Control Word PPEN, CIR1EN and CIR2EN bits
are all zero.
When a subaddress or mode command uses the in-
dexed data buffer mode, its 4-word descriptor block in
the Descriptor Table is defined as follows:
If Descriptor Word 1 is stored at memory address N, De-
scriptor Word 2 is stored at address N+1, and the other
two words are stored at addresses N+2 and N+3.
As the name implies, all message information and data
is stored in a single buffer, indexed by descriptor word
Data Pointer A. The descriptor Control Word DPB bit
is “don’t care”. The host initializes the desired message
count in descriptor INDX word. During message pro-
cessing, the device retrieves or stores data words from
the address specified by descriptor Data Pointer A, auto-
matically incrementing the pointer address as words are
read or stored. Data Pointer A is updated during com-
mand post-processing with the current buffer address
unless the message index count in descriptor INDX
(word 3 of descriptor block) decrements to zero upon
completion of the message. Figure 20 is a general illus-
tration of indexed single buffer mode. Figure 21 shows
a specific example.
To set up a terminal subaddress to buffer multiple mes-
sages, the host writes the desired index count (INDX)
to subaddress descriptor word 3. The initial INDX value
ranges from zero to 3FF hex (1023) messages. The de-
vice decrements the INDX count each time an error-free
message is transacted, and the data pointer is updated
to the first memory address to be used for the next mes-
sage. If INDX decrements from one to zero and Control
Word IXEQZ bit 15 is asserted, the IXEQZ bit is set in
the Interrupt Pending Register. If the corresponding bit
in the Interrupt Enable Register is asserted, an INTMES
interrupt is generated when INDX decrements from one
to zero.
INDX counter decrement does not occur if the command
was illegalized or if INDX already equals zero. Once
Descriptor Word 1
Descriptor Word 2
Descriptor Word 3
Descriptor Word 4
Control Word
Data Pointer A
INDX Index Word
Broadcast Data Pointer
HOLT INTEGRATED CIRCUITS
HI-6130, HI-6131
195
INDX equals zero, further commands will overwrite the
last-written data buffer block and the data pointer value
is not updated after successful message completion.
When using Index Mode with a non-zero INDX value,
the host must remember the initial Data Pointer A ad-
dress. The Data Pointer A word is not automatically re-
initialized to the buffer start address when INDX decre-
ments from 1 to 0.
20.4.1. Single Message Mode
When Index Mode is initialized with an INDX value of
zero, the subaddress or mode code is operating in “Sin-
gle Message Mode”. Here, the same data block is re-
peatedly over-read (for transmit data) or overwritten (for
receive or broadcast data). The DPA pointer is not up-
dated at the end of each message. The chief advantage
of single message mode is simplicity. In comparison to
other data buffering options, the single message buffer
uses an absolute minimum amount of memory space.
The IXEQZ interrupt cannot be used for this scheme
(INDX is always zero) but IWA interrupts may be used.
Single message mode is best suited to synchronous
data transfer where the host processor can reliably read
or write new message data prior to the start of the next
message to the same subaddress or mode code.
20.4.2. Broadcast Message Handling in Index
For MIL-STD-1553B Notice II compliance, a remote ter-
minal should be capable of storing data from broadcast
messages separately from non-broadcast message
data. Some applications may not include this require-
ment. The standard does not stipulate where data sep-
aration should occur (e.g., within the RT or within the
external host) so the device supports alternative strate-
gies.
When the NOTICE2 bit is logic 1 in Configuration Regis-
ter 1, broadcast message data is stored in a broadcast
data buffer assigned for the subaddress or mode com-
mand. Each subaddress or mode command must have
an assigned, valid non-zero broadcast buffer address.
Non-broadcast message data is stored in Data Buffer A.
There are two ways to deal with broadcast messages in
indexed buffer mode:
Option 1 for Index Mode Broadcast Messages:
The first alternative isolates broadcast message informa-
tion in the broadcast data buffer. If the descriptor Control
Word IBR bit and Interrupt Enable Register IBR bit are
both set, reception of broadcast messages generates an
INTMES interrupt to the host. The broadcast data buffer
Mode