hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 131

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

16.5. IMT Packet Maximum Message Count Register (0x002A)
This 16-bit register is read-write and is maintained by the host. This register is cleared after MR pin master reset but
is not affected by MT soft reset, when the MTRESET bit is asserted in the Master Status and Reset Register, 0x0001.
This register only applies when the monitor is configured for IRIG-106 Chapter 10 operational mode, which is
when IMT bit 0 is initialized to logic 0 in the MT Configuration Register 0x0029. In this mode, monitored message data
is stored in “data packets” in the monitor stack. The HI-613x IMT finalizes the unfinished packet when the number of
MIL-STD-1553 messages in the packet reaches the value in this register. If register value is zero, this criteria is not
used for determination of end-of-packet.
16.5.1. Practical IRIG-106 packet message count considerations
IRIG-106 Chapter 10 stipulates a maximum allowable time interval of 100 ms for any data packet. The maximum
number of packet messages occurs when the BC continuously transmits back-to-back broadcast mode code
commands without data, each with the minimal allowable intermessage gap of 4 µs, yielding 2 µs dead time between
commands. This results in repeating message transmission every 22 µs. Therefore the maximum packet message
count is (100 ms / 22 µs) or 4,545 messages occurring in the maximum allowed 100 ms packet interval. Therefore, for
strict compliance with IRIG-106, the maximum attainable packet message count is 4,545 decimal.
The HI-613x device can be configured to record packet times exceeding the IRIG-106 limit. Without regard for maximum
packet time allowed by IRIG-106, the maximum message count governed by HI-613x RAM capacity is a lower value. If
the HI-613x is configured as IMT only, the maximum contiguous RAM space is 0x7FFF – 0x01BF = 0x7E40 = 32,320
words. Maximum message storage space occurs when the HI-613x IMT is configured to provide the data Packet Body,
without packet header or trailer. 14 words are used for packet header, leaving 32,306 words for messages. If the BC
continuously transmits back-to-back broadcast mode code commands without data, each message consumes 8 words
of buffer space. This unlikely repeating message sequence yields the highest packet possible message count for a
RAM-limited HI-613x monitor, which is 32,306 / 8 = 4,038 messages. Transmit and receive subaddress commands
typically require far more than 8 stored words per MIL-STD-1553 message, so normal bus traffic will probably fill the
IMT Stack far in advance of 4,000 messages.
16.6. IMT Packet Maximum 1553 Word Count Register (0x002B)
This 16-bit register is read-write and is maintained by the host. This register is cleared after MR pin master reset but
is not affected by MT soft reset, when the MTRESET bit is asserted in the Master Status and Reset Register, 0x0001.
This register only applies when the monitor is configured for IRIG-106 Chapter 10 operational mode, which is
when IMT bit 0 is initialized to logic 0 in the MT Configuration Register 0x0029. In this mode, monitored message data
is stored in “data packets” in the monitor stack. The HI-613x IMT finalizes the unfinished packet when the number of
16-bit MIL-STD-1553 message words in the packet reaches the value in this register. This word count is comprised
of BC command, RT status and message data words. It excludes IRIG-106 header and trailer (if used) and message
block data words and time stamp words. If the register value is zero, this register is not used for determination of end-
MSB
MSB
15 14 13 12 11 10
15 14 13 12 11 10
0
0
0
0
0
0
0
0
0
0
0
0
Register Value
Register Value
0
9
0
9
0
8
0
8
RW
RW
7
7
0
0
0
6
0
6
0
0
5
5
4
4
0
0
0
3
0
3
HOLT INTEGRATED CIRCUITS
0
0
2
2
HI-6130, HI-6131
0
1
0
1
LSB
LSB
0
0
0
0
MR Reset
Host Access
Bit
MR Reset
Host Access
Bit
131