hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 33

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

9.2.
This 16-bit register has a combination of read only and read-write bits. This register is cleared after MR pin master
reset, but is unaffected by assertion of MTRESET, RT1RESET or RT2RESET register bits.
15 14 13 12 11 10
Bit No.
Bit No.
0
15
14
13
12
1
0
R
0
Master Status and Reset Register (0x0001)
0
Mnemonic
IMTA
Reserved
Mnemonic
READY
Reserved
AUTOEN
MTRESET
0
RW
0
0
0
9
0
8
R/W
R/W
R/W
R/W
R
R
R
7
-
0
0
6
Reset
Reset
R
0
5
0
-
0
0
0
0
4
0
0
3
Function
Indicate MT Activity.
When this bit equals 0, the ACTIVE status output is not asserted for Bus
Monitor activity, unless the monitored message involves another on-
chip terminal). When this bit equals 1, enabled Bus Monitor activity is
logically-ORed with the activity of the other on-chip devices to determine
ACTIVE status; the ACTIVE output is asserted during such Bus Monitor
activity, whether or not the monitored message involves another on-chip
terminal.
This bit is not used and reads logic 0.
HOLT INTEGRATED CIRCUITS
Function
The READY output pin reflects the state of this register bit. READY
is low when auto-initialization, a soft reset caused by bit 12~10
assertion, or built-in test is underway. Host access to device registers
or RAM is locked out while READY is low. While READY = 0, any host
read access returns the value in this register, regardless of address
provided. When READY goes high, the host may access registers and
RAM.
This bit is not used.
Auto-Initialization Enable Status.
This bit reflects the state of the AUTOEN input pin that applied at the
rising edge on the MR Master Reset input pin. If the register bit is high,
auto-initialization was performed following MR reset.
Bus Monitor Reset.
When written to logic 1, this bit initiates Bus Monitor reset. This bit
remains high until reset is complete. While this bit remains high, the
READY output pin and register bit 15 are held low, host RAM and
register access is suspended. While READY = 0, any host read access
returns the value in this register, regardless of address provided. Upon
reset completion, this bit self-clears to logic 0, the READY pin goes
high and host read/write access is restored.
0
2
HI-6130, HI-6131
1
0
0
0
MR Reset
Host Access
Bit
33