hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 222

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

within the 512-word Descriptor Table address range.
For fastest read access under all conditions, the user
can set host processor bus timing (by adjusting proces-
sor wait states for the chip select assigned to the HI-
6130) to match the faster read cycle time for prefetched
data, while the HI-6130 WAIT output adds one or more
additional wait states for the slower initial read cycle.
Timing diagrams for bus read and write operations are
shown in the Section Electrical Characteristics. Sep-
arate diagrams show “Intel style” and “Motorola style”
control interfaces.
24.2. HI-6131 Serial Peripheral Interface
In the HI-6131, internal RAM and registers occupy a 32K
x 16 address space. The lowest 80 addresses access
registers and the remaining addresses access RAM
locations. Timing is identical for register operations and
RAM operations via the serial interface, and read and
write operations have likewise identical timing.
24.2.1. Serial Peripheral Interface (SPI) Basics
The HI-6131 uses an SPI synchronous serial interface
for host access to registers and RAM. Host serial
communication is enabled through the Chip Enable
(CE) pin, and is accessed via a three-wire interface
consisting of Serial Data Input (SI) from the host, Serial
Data Output (SO) to the host and Serial Clock (SCK). All
programming cycles are completely self-timed, and no
erase cycle is required before write.
Figure 26. Generalized Single-Byte Transfer Using SPI Protocol. SCK is Shown for SPI Modes 0
SCK (SPI Mode 0)
SCK (SPI Mode 3)
SI
SO
CE
High Z
MSB
MSB
0
0
1
1
HOLT INTEGRATED CIRCUITS
HI-6130, HI-6131
2
2
and 3
222
3
3
The SPI (Serial Peripheral Interface) protocol specifies
master and slave operation; the HI-6131 operates as an
SPI slave.
The SPI protocol defines two parameters, CPOL (clock
polarity) and CPHA (clock phase). The possible CPOL-
CPHA combinations define four possible “SPI Modes.”
Without describing details of the SPI modes, the HI-
6131 operates in the two modes where input data for
each device (master and slave) is clocked on the rising
edge of SCK, and output data for each device changes
on the falling edge. These are known as SPI Mode 0
(CPHA = 0, CPOL = 0) and SPI Mode 3 (CPHA = 1,
CPOL = 1). Be sure to set the host SPI logic for one of
these modes.
The difference between SPI Modes 0 and 3 is the idle
state for the SCK signal, which is logic 0 for Mode 0
state and logic 1 for Mode 3 state (see Figure 26). There
is no configuration setting in the HI-6131 to select SPI
Mode 0 or Mode 3 because compatibility is automatic.
Beyond this point, the HI-6131 data sheet only shows
the SPI Mode 0 SCK signal in timing diagrams.
The SPI protocol transfers serial data as 8-bit bytes.
Once CE chip enable is asserted, the next 8 rising edg-
es on SCK latch input data into the master and slave de-
vices, starting with each byte’s most-significant bit. The
HI-6131 SPI can be clocked at 16 MHz.
4
4
5
5
6
6
LSB
LSB
7
7
High Z