hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 142

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

18. REGISTERS USED BY REMOTE TERMINALS RT1 AND RT2
In addition to the registers described here, HI-6131 Remote Terminals RT1 and RT2 also utilize one or more Memory
Address Pointer registers (described in Section 9.8) for managing SPI read/write operations. This comment does not
apply for parallel bus interface HI-6130 designs.
18.1. Remote Terminal 1 (RT1) Configuration Register (0x0017)
15 − 14
Bit No.
13
12
Remote Terminal 2 (RT2) Configuration Register (0x0020)
Mnemonic
RTTO1:0
RTINHA
RTINHB
R/W
R/W
R/W
R/W
Reset
0
0
0
HOLT INTEGRATED CIRCUITS
Function
RT-RT Time Out Select.
This 2-bit field selects the “no response” time-out delay for RT-to-RT
receive commands from four available selections:
For RT-RT commands, time out delay is measured per Figure 8 in the
RT Validation Test Plan, SAE AS4111. That is, from mid-parity of the
receive command to mid-sync of the first received data word. This
interval includes 20µs each for the embedded transmit command word
and transmit-RT status word within this span.
RT Bus A Inhibit.
If this bit is logic 1, Bus A for this RT is inhibited, as defined by the
BSDTXO bit in register 0. The BSDTXO bit offers two options: inhibit
transmit and receive, or inhibit only transmit. Setting the RTINHA bit
inhibits Bus A for just this RT, while allowing normal Bus A operation by
the BC or the other RT.
Note: If this bit is logic 0, Bus A is not inhibited here but its operation
may otherwise be globally inhibited by logic 1 at the TXINHA pin, or logic
1 at the TXINHA bit in the Master Status & Reset Register.
RT1 Bus B Inhibit.
If this bit is logic 1, Bus B for this RT is inhibited, as defined by the
BSDTXO bit in register 0. The BSDTXO bit offers two options: inhibit
transmit and receive, or inhibit only transmit. Setting the RTINHB bit
inhibits Bus B for just this RT, while allowing normal Bus B operation by
the BC or the other RT.
Note: If this bit is logic 0, Bus B is not inhibited here for this RT but its
operation may otherwise be globally inhibited by logic 1 at the TXINHB
pin, or logic 1 at the TXINHB bit in the Master Status & Reset Register.
HI-6130, HI-6131
Bit 15:14
00
01
10
11
142
Bus Dead Time
138μs
15μs
20μs
58μs
RT-RT Time Out
100μs
180μs
57μs
62μs