hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 38

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

9.5.
9.5.1.
9.5.2.
9.5.3.
These three registers govern hardware interrupt behavior. As explained on the preceding page, bits 2-0 in the Hardware
Pending Interrupt Register are set whenever interrupt bits are set in the other three pending interrupt registers (RT,
MT and BC). The table below first describes the common bits 15-3 in all three registers and then describes register-
to-register differences for bits 2-0.
15 14 13 12 11 10 9
15 14 13 12 11 10 9
15 14 13 12 11 10 9
Bit No.
0
0
0
15
1
0
1
Hardware Interrupt Registers
1
0
1
Hardware Interrupt Enable Register (0x000F)
Hardware Pending Interrupt Register (0x0006)
Hardware Interrupt Output Enable Register (0x0013)
Mnemonic
HSPIINT
0
0
0
0
0
0
0
0
0
RW
RW
R
0
0
0
8
8
8
0
0
0
R/W
R/W
7
7
7
0
0
0
6
6
6
0
0
0
Reset
0
5
0
5
0
5
0
4
4
4
1
0
1
3
3
3
1
0
1
HOLT INTEGRATED CIRCUITS
Function
Host SPI Interrupt.
This bit only applies to HI-6131 with SPI host interface, which operates
in SPI Slave mode. An unexpected number of SCK clock pulses
occured during a SPI transaction.
0
2
0
2
0
2
HI-6130, HI-6131
R
R *
R
1
1
1
0
0
0
0
0
0
0
0
0
MR Reset
Host Access
Bit
MR Reset
Host Access
Bit
MR Reset
Host Access
Bit
38
* Bits 2 - 0 are read-only and cannot be set by host.
* Bits 2 - 0 are set for pending interrupts
* Bits 2 - 0 are read-only and cannot be set by host.
from RT (RT1 or RT2), MT or BC