hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 101

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

13. SIMPLE MONITOR TERMINAL (SMT) REGISTER DESCRIPTION
In addition to the registers described here, a HI-6131 SMT Bus Monitor also utilizes one or more Memory Address
Pointer registers (described in Section 9.8) for managing SPI read/write operations. This comment does not apply for
parallel bus interface HI-6130 designs.
13.1. SMT Configuration Register (0x0029)
15 − 14
11 − 10
15 14 13 12 11 10 9
Bit No.
0
RW
13
12
0
W
0
Mnemonic
MTTO1:0
Reserved
GCHK
Reserved
0
0
0
0
0
8
R/W
R/W
R/W
R/W
W
7
0
RW
0
6
Reset
0
5
0
0
0
0
4
0
0
3
HOLT INTEGRATED CIRCUITS
Function
MT Time Out Select.
This 2-bit field selects the Monitor “no response” time-out delay from
four available selections. Excluding RT-RT commands, the delay is
measured from command word mid-parity bit to status word mid-sync.
For RT-RT commands, time out delay is measured per Figure 8 in the
RT Validation Test Plan, SAE AS4111. That is, from mid-parity of the
receive command to mid-sync of the first received data word. This adds
40µs for the embedded transmit command word and transmit-RT status
word within this interval.
Bit 13 is not used by the bus monitor operating in SMT mode.
Initialize this bit to logic 0.
Gap Check.
When this bit equals 1, the monitor evaluates inter-message gaps and
RT response times for a minimum preceding bus dead time of 2 µs.
This dead time corresponds to an inter-message gap of 4µs, measured
per MIL-STD-1553, from mid-parity zero crossing of the preceding
word, to mid-sync zero crossing of the following word. A minimum gap
time violation results in a Format Error in the Block Status Word for the
message.
When this bit equals 0 (recommended), the monitor does not check for
short inter-message gap times.
Bits 11-10 are not used by the bus monitor operating in SMT mode.
Initialize these bits to logic 0.
Bit 15:14
0
2
HI-6130, HI-6131
00
01
10
11
0
1
0
0
MR Reset
Host Access
Bit
101
138μs
Dead
Time
16μs
21μs
80μs
Bus
(excludes RT-
Time Out
140μs
18μs
23μs
82μs
RT)
RT-RT Time Out
122μs
180μs
61μs
66μs