hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 48

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

The four memory address pointer registers are:
MAP1 Memory Address Pointer Register
MAP2 Memory Address Pointer Register
MAP3 Memory Address Pointer Register
MAP4 Memory Address Pointer Register
These 16-bit registers are read-write and are fully maintained by the host. These registers are cleared after MR pin
master reset, but are unaffected by assertion of RT1RESET, RT2RESET or MTRESET bits in the Master Status and
Reset Register (0x0001).
Each of these registers has a unique SPI op code that reads the MAP value in the register, and another op code that
writes a new MAP value into the register. See SPI op code table. The host selects the active MAP register by writing
the MAPSEL (memory address pointer select) bits 11-10 in the Master Configuration Register (see Section 9.1), or
by using the four defined “MAP Select” SPI op codes, described in Section XX. The active MAP register contains the
memory address used for SPI read write access to registers and RAM.
Please refer to section “SPI Interface” for a full description of the interface and the SPI instruction op codes.
MSB
15 14 13 12 11 10
0
0
0
0
0
0
Register Value
0
9
0
8
RW
7
0
0
6
0
5
4
0
0
3
HOLT INTEGRATED CIRCUITS
0
2
HI-6130, HI-6131
0
1
0x000B
0x000C
0x000D
0x000E
LSB
0
0
MR Reset
Host Access
Bit
48