hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 71

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

11. BUS CONTROLLER REGISTER DESCRIPTION
In addition to the registers described here, a HI-6131 Bus Controller also utilizes one or more Memory Address Pointer
registers (described in Section 9.8) for managing SPI read/write operations. This comment does not apply for parallel
bus interface HI-6130 designs.
11.1. BC (Bus Controller) Configuration Register (0x0032)
15 − 14
15 14 13 12 11 10 9
Bit No.
0
0
0
Mnemonic
BCTO1:0
0
0
0
0
8
0
RW
R/W
R/W
7
0
0
6
Reset
0
5
0
4
0
0
3
HOLT INTEGRATED CIRCUITS
Function
BC Time Out Select.
This 2-bit field selects the BC “no response” time-out delay from four
available selections. Excluding RT-RT commands, response delay is
measured from command word mid-parity bit to status word mid-sync:
For RT-RT commands, time out delay is measured per Figure 8 in the
RT Validation Test Plan, SAE AS4111. That is, from mid-parity of the
receive command to mid-sync of the first received data word. This
adds 42µs for the embedded parity half-bit, transmit command word,
transmit-RT status word and data half-sync within this interval:
*Note: per RT Validation Test Plan, Fig. 8.
All time out select values have –100ns / +500ns tolerance.
0
2
HI-6130, HI-6131
Bit 11:10
Bit 11:10
0
1
00
01
10
11
00
01
10
11
0
0
Bit
MR Reset
Host Access
71
TxRT Bus Dead
Bus Dead Time
138μs
138μs
Time
15μs
20μs
58μs
18μs
23μs
58μs
Time Out (excludes RT-RT)
RT-RT Time Out*
140μs
100μs
180μs
17μs
22μs
60μs
60μs
65μs