hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 236

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

Circumstances for
Received Message
Valid receive
command followed
by invalid data word
(Manchester, parity
or bit count error).
Superseded Message:
Terminal receives an
incomplete message
interrupted by a gap
of at least 3.5 us,
followed by a new
valid command on
the same bus or
on the other bus
OR
Terminal is transacting
a transmit message on
one bus and receives
the start of a valid
command on the other
bus.
Terminal is Busy for a
valid receive command
either globally (BUSY
bit set in Status Word
Bits register) or in
response to a particular
valid receive command
(MKBUSY bit set in the
command’s Descriptor
Table control word.)
Terminal is Busy for a
valid transmit
command
either globally (BUSY
bit set in Status Word
Bits register) or in
response to a particular
valid receive command
(MKBUSY bit set in the
command’s Descriptor
Table control word.)
Terminal Response to
Received Command
No terminal response.
Set Status Word ME bit,
If broadcast, also set
Status Word BCR bit.
Terminal aborts processing
for first message and
responds in full to the
second (superseding)
message. The Status
Word BCR bit reflects
broadcast status for:
the second command,
unless second command
is MC2 (transmit status)
or MC18 (transmit last
command).
Busy bit is set in the 1553
Status Bits register. Status
Word is transmitted,
unless broadcast. If
broadcast, the BCR bit
in Status Word is also
set. After message
completion, data words
received are stored in
the data buffer assigned
by the receive subaddress
Descriptor Table entry.
Busy bit is set in the 1553
Status Bits register. If not
broadcast, Status Word is
transmitted without data.
If broadcast, the BCR bit
in Status Word is also
set.
HOLT INTEGRATED CIRCUITS
HI-6130, HI-6131
236
Bits Updated
in Descriptor
Control Word
DBAC bit set.
BCAST bit
updated.
DPB bit toggles.
No change
to superseded
command’s
Control Word.
For superseding
command’s
Control Word:
DBAC bit set.
BCAST bit
updated
DPB bit toggles.
DBAC bit set.
BCAST bit
updated.
DPB bit toggles.
DBAC bit set.
BCAST bit
updated,
(mode
commands
with T/R = 1)
DPB bit toggles
Bits Updated in Data
Buffer Msg Info Word
MERR bit set.
BUSID bit updated.
IWDERR bit set.
ILCMD bit reset.
RTRT bit updated.
(Other error bits reset.)
No Msg Info
Word written for
the superseded
command.
For superseding
command’s
data buffer, a
normal CS update:
BUSID bit updated.
MERR bit reset.
ILCMD bit reset.
RTRT bit updated.
(All error bits reset.)
WASBSY bit set.
BUSID bit updated.
MERR bit reset.
ILCMD bit reset.
RTRT bit updated.
(All error bits reset.)
WASBSY bit set.
BUSID bit updated.
MERR bit reset.
ILCMD bit reset.
RTRT bit updated.
(All error bits reset.)
Interrupt
Options
MERR
IWA
IBR
None for
super-
seded
command
IWA
IBR
(IXEQZ)
IWA
IBR
IWA
IBR