hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 15

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

2. FEATURE OVERVIEW
2.1.
The HI-613x is configurable to operate as a Bus Controller
(BC). The BC is a programmable message-sequencing
device for control in MIL-STD-1553B applications.
Programmed using a set of 28 instruction op codes,
the BC greatly reduces the host’s processing workload.
The BC can optionally use a 16- or a 32-bit time base,
clocked from a choice of six internally generated clocks,
or an external time base clock. Special BC op codes
manage all 32-bit time base functions. One internally
generated BC time base option clocks the 32-bit BC
time counter coincident with the upper 32-bits of the 48-
bit MIL-STD-1760 aircraft system time.
The programmable HI-613x Bus Controller autonomously
supports multi-frame message scheduling, message
retry schemes, storage of message data, asynchronous
message insertion and status /error reporting to the host
processor.
2.2.
The HI-613x is configurable to operate one as or two
Remote Terminals. The RTs are modeled after the popular
Holt HI-6120/21 Remote Terminal. The two Remote
Terminals operate with independent characteristics,
each RT having fully separate RAM structures (e.g.,
descriptor and illegal command tables) and independent
configuration and status registers. RAM buffer options
include single, double and 2 circular buffer choices. The
two RTs can be reset and reinitialized independently.
The full benefit of two autonomous RTs is achieved
while using the same complexity and circuit board area
as a single Remote Terminal.
2.3.
The Bus Monitor Terminal (MT) passively records MIL-
STD-1553 bus activity. Message commands, terminal
responses and message data are stored in internal RAM,
using either one or two data stacks. Single- and dual-
stack MT modes are targeted for different applications.
When operating in dual-stack mode, the MT maintains
separate command and data stacks. The single-stack
HI-613x MT offers expanded message status flags to
minimize host processing. The MT can utilize 16- or 48-
bit time tags with a range of clocking options.
Single-stack HI-613x Bus Monitor operation is designed
to meet data recording requirements of Telemetry
Standard RCC Document 106-07, Chapter 10. This “IRIG
Bus Controller Operation
Remote Terminal Operation
Monitor Terminal Operation
HOLT INTEGRATED CIRCUITS
HI-6130, HI-6131
15
106 Chapter 10” data recorder uses 48-bit relative time
stamping, having 10MHz (100ns) resolution. Message
time stamps occur at one of three selectable message
progress points. Several error handling schemes are
available. Bus Monitor interrupts notify the host when
stack rollover occurs, or when a user-programmed stack
level has been reached. The single-stack HI-613x MT
stores message records in the assigned stack using
IRIG 106 “packet body” format. The device can optionally
generate complete IRIG 106 packets, including full
packet headers and trailers meeting IRIG 106 Chapter
10 requirements.
2.4.
Host interrupts can originate from device hardware or
any of the enabled terminal devices (up to 4 devices).
A circular 64-word Interrupt Log Buffer retains interrupt
information from the last 32 interrupts, while the
hardware maintains a count of occurring interrupts since
the previous host buffer service.
Hardware-assisted interrupt decoding provides quick
identification of the interrupt source by terminal device:
BC, MT, RT1, RT2 or hardware. When a hardware
interrupt occurs (e.g., Bus A Loopback Failure), a
Pending Hardware Interrupt register bit explicitly
identifies the interrupt source. For interrupts from BC,
MT or RT, the three low-order bits in the same register
identify the specific interrupt register (or registers) with
pending interrupts: that is, the BC, MT or RT Pending
Interrupt registers.
2.5.
After hardware Master Reset, there are two HI-
613x initialization methods: host initialization or self-
initialization from external serial EEPROM. For host
initialization, the host processor uses its bus interface
or 4-wire SPI to load HI-613x registers and initialize
tables, data buffers, etc. in internal static RAM. For self-
initialization, the device uses setup information contained
within an external serial EEPROM. A dedicated 4-wire
SPI port reads data from the serial EEPROM and writes
it to registers and RAM. Error checking is performed,
looking for data mismatch or an EEPROM checksum
error.
Individual 1553 terminal devices (BC, MT, RT1 or RT2)
can be re-initialized from the serial EEPROM by writing
to the Reset Initialization Register.
Interrupts
Reset and Initialization